# US 2014/0197863 A1 · Placement of storage cells on an integrated circuit > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2014/0197863 A1 - Document ID: US20140197863A1 - Status: Published application - Kind: A1 - Application number: 13/741,600 - Filed: 2013-01-15 - Published: 2014-07-17 - Earliest claimed: 2013-01-15 - Assignees: International Business Machines Corporation - Applicants: International Business Machines Corporation - Inventors: William V. Huott; Kevin W. Kark; John G. Massey; K. Paul Muller; David L. Rude; David S. Wolpert - Web page: https://patentgrep.com/patent/US20140197863A1 ## CPC - H03K 19/003: Modifications for increasing the reliability {for protection} - H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M) ## Abstract A method for configuring the placement of a plurality of storage cells on an integrated circuit includes grouping the plurality of storage cells into a plurality of words, where each of the plurality of words is protected by an error control mechanism. The method also includes placing each of the storage cells on the integrated circuit such that a distance between any two of the storage cells belonging to one of the plurality of words is greater than a minimum distance. The minimum distance is configured such that a probability of any of the plurality of words experiencing multiple radiation induced errors is below a threshold value. ## Claims ### Claim 1 A method for configuring the placement of a plurality of storage cells on an integrated circuit comprising: grouping the plurality of storage cells into a plurality of words, wherein each of the plurality of words is protected by an error control mechanism; placing each of the storage cells on the integrated circuit such that a distance between any two of the storage cells belonging to one of the plurality of words is greater than or equal to a minimum distance; and wherein the minimum distance is configured such that a probability of any of the plurality of words experiencing multiple radiation induced errors is below a threshold value. ### Claim 2 (depends on 1) The method of claim 1, wherein the distance is a function of an angle between two storage cells. ### Claim 3 (depends on 1) The method of claim 1, wherein the distance includes a first distance in an insensitive direction and a second distance in a sensitive direction separating two storage cells. ### Claim 4 (depends on 1) The method of claim 1, wherein the error control mechanism is a parity protection bit. ### Claim 5 (depends on 1) The method of claim 1, wherein the error control mechanism is an error correction code. ### Claim 6 (depends on 1) The method of claim 1, wherein the threshold value is one tenth of a percent of all particle induced soft errors. ### Claim 7 (depends on 1) The method of claim 1, wherein the minimum distance is at least twice a length of a storage cell. ### Claim 8 A method for configuring the placement of a plurality of storage cells on an integrated circuit comprising: determining a sensitive direction and an insensitive direction of the plurality of storage cells; grouping the plurality of storage cells into a plurality of words, wherein each of the plurality of words is protected by an error control mechanism; placing each of the storage cells on the integrated circuit such that a distance in the insensitive direction between any two of the storage cells belonging to one of the plurality of words is greater than a minimum distance; and wherein the minimum distance is configured such that a probability of any of the plurality of words experiencing multiple radiation induced errors is below a threshold value. ### Claim 9 (depends on 8) The method of claim 8, wherein the insensitive direction is a direction perpendicular to a width of a gate conductor of the storage cells. ### Claim 10 (depends on 8) The method of claim 8, wherein the error control mechanism is a parity protection bit. ### Claim 11 (depends on 8) The method of claim 8, wherein the error control mechanism is an error correction code. ### Claim 12 (depends on 8) The method of claim 8, wherein the minimum distance is configured to be at least twice a length of the storage cell in the insensitive direction. ### Claim 13 (depends on 8) The method of claim 8, wherein the threshold value is one tenth of a percent. ### Claim 14 An integrated circuit comprising: a plurality of storage cells grouped into a plurality of words, wherein each of the storage cells on the integrated circuit is disposed such that a distance between any two of the storage cells belonging to one of the plurality of words is greater than a minimum distance; and an error control mechanism configured to protect each of the plurality of words; wherein the minimum distance is configured such that a probability of any of the plurality of words experiencing multiple radiation induced errors is below a threshold value. ### Claim 15 (depends on 14) The integrated circuit of claim 14, wherein the minimum distance includes a distance in an insensitive direction and a distance in a sensitive direction separating two storage cells. ### Claim 16 (depends on 15) The integrated circuit of claim 15, wherein the insensitive direction is a direction perpendicular to a width of a gate conductor of the storage cells. ### Claim 17 (depends on 14) The integrated circuit of claim 14, wherein the error control mechanism is a parity protection bit. ### Claim 18 (depends on 14) The integrated circuit of claim 14, wherein the error control mechanism is an error correction code. ### Claim 19 (depends on 16) The integrated circuit of claim 16, wherein the minimum distance is configured to be at least twice a length of the storage cell in the insensitive direction.