# US 2014/0197856 A1 · Self testing fault circuit apparatus and method

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- Number: US 2014/0197856 A1
- Document ID: US20140197856A1
- Status: Published application
- Kind: A1
- Application number: 14/030,999
- Filed: 2013-09-18
- Published: 2014-07-17
- Earliest claimed: 2008-01-29
- Assignees: Leviton Manufacturing Co., Inc.
- Applicants: Leviton Manufacturing Co., Inc.
- Inventors: Michael OSTROVSKY; Adam KEVELOS
- Web page: https://patentgrep.com/patent/US20140197856A1

## CPC

- G01R 31/2884: {using dedicated test connectors, test elements or test circuits on the IC under test (G01R31/2855 takes precedence)}
- G01R 31/3277: {of low voltage devices, e.g. domestic or industrial devices, such as motor protections, relays, rotation switches}
- H02H 3/335: {the main function being self testing of the device}
- G01R: MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES (indicating correct tuning of resonant circuits H03J3/12)
- H02H: EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS (indicating or signalling undesired working conditions G01R, e.g. G01R31/00, G08B; locating faults along lines G01R31/08; emergency protective devices H01H)

## Abstract

A process for self testing a fault circuit includes disabling an actuator, performing a self test by creating a simulated fault signal across at least a portion of a half cycle of a first polarity and across at least a portion of a hall cycle of a second polarity, and determining whether the self test was successful.

## Claims

### Claim at position 1

1-34. (canceled)

### Claim 35

A process for self testing a fault circuit comprising:
a) disabling an actuator;
b) performing a self test by creating a simulated fault signal across at least a portion of a half cycle of a first polarity and across at least a portion of a half cycle of a second polarity; and
c) determining whether the self test was successful.

### Claim 36 (depends on 35)

The process as in claim 35, wherein said step of disabling said actuator comprises preventing a signal from reaching said actuator.

### Claim 37 (depends on 36)

The process as in claim 36, wherein said step of disabling said actuator comprises blocking a SCR from receiving a fault signal.

### Claim 38 (depends on 35)

The process as in claim 35, wherein said step of performing a self test comprises creating a current imbalance between a phase and neutral line.

### Claim 39 (depends on 35)

The process as in claim 35, wherein said step of performing a self test comprises:
creating a current imbalance by activating at least one transistor to cause current to flow from at least one electrical conductor configured to be read by at least one fault sensor, wherein said current imbalance is read by said at least one fault sensor.

### Claim 40 (depends on 35)

The process as in claim 35, wherein said step of performing a self test comprises:
a) detecting a zero crossing of an AC line signal;
b) timing a self test to occur during at least a portion of a first half polarity and during at least a portion of a second half cycle of opposite polarity.

### Claim 41 (depends on 40)

The process as in claim 40, further comprising the step of timing a self test during an alternate half cycle of alternating current.

### Claim 42 (depends on 41)

The process as in claim 41, wherein said step of timing a self test during at least one half cycle of alternating current comprises timing a self test during only a portion of said at least one half cycle of alternating current.

### Claim 43 (depends on 35)

The process as in claim 35, further comprising the step of controlling a duration of a self test.

### Claim 44 (depends on 43)

The process as in claim 43, wherein said step of controlling a duration of a self test comprises controlling said duration based upon an amount of power fed into a capacitor.

### Claim 45 (depends on 44)

The process as in claim 44, wherein said step of controlling a duration of a self test comprises controlling a discharge rate of power of said capacitor.

### Claim 46 (depends on 35)

The process as in claim 35, wherein said step of detecting a fault includes receiving a signal from a fault sensor indicating the presence of a fault.

### Claim 47 (depends on 35)

The process as in claim 35, wherein said step of indicating a result of said self test comprises providing a light indication for said self test.

### Claim 48 (depends on 35)

The process as in claim 35, wherein said step of indicating a result of said self test comprises providing an audio indication for said self test.

### Claim 49 (depends on 35)

The process as in claim 35, wherein said step of indicating a result of said self test comprises indicating whether a self test is performed successfully.

### Claim 50 (depends on 35)

The process as in claim 35, wherein said step of indicating a result c said self test comprises indicating whether a set of contacts have tripped.

### Claim 51 (depends on 35)

The process as in claim 35, further comprising the step of determining an overcurrent condition.

### Claim 52 (depends on 35)

The process as in claim 35, further comprising the step of determining overvoltage condition.

### Claim 53 (depends on 35)

The process as in claim 35, further comprising the step of permanently removing the fault circuit from operation by opening a fusable link along at least one of said phase line and said neutral line.

### Claim 54 (depends on 43)

The process as in claim 43, further comprising the step of controlling a duration of the self test based upon the presence of an external fault.

### Claim 55 (depends on 54)

The process as in claim 54, wherein said step of controlling the duration of the self test comprises receiving an external fault comprising a ground fault.

### Claim 56 (depends on 55)

The process as in claim 55, wherein said step of controlling a duration of a self test comprises removing power from a capacitor.

### Claim 57 (depends on 56)

The process as in claim 56, wherein said step of receiving an external fault comprises providing power from said external fault to said capacitor to reduce a time for completing said step of performing a self test.

### Claim 58 (depends on 56)

The process as in claim 56, further comprising the step of actuating an actuator to remove power to a load side when an external fault exists beyond said step of providing a self test.

### Claim 59 (depends on 43)

The process as in claim 43, further comprising the step of determining when a fault signal is received to determine whether an external fault is occurring.

### Claim 60 (depends on 59)

The process as in claim 59, further comprising the step of actuating said actuator to remove power to a load side in response to determining that an external fault exists.

### Claim 61 (depends on 43)

The process as in claim 43, further comprising the step activating a transistor to control the duration of a self test.

### Claim 62 (depends on 61)

The process as in claim 61, wherein said step of activating a transistor, comprises turning a transistor on, and wherein the process further includes the step of discharging a capacitor, wherein said step of turning a transistor on, creates a discharge path for said capacitor, to create a shorter test cycle.

### Claim 63 (depends on 62)

The process as in claim 62, wherein after said step of discharging a capacitor is completed, said step of disabling an actuator is completed.

### Claim at position 31

64-70. (canceled)

### Claim 71

A method for testing a fault circuit comprising the following steps:
a) periodically preventing an actuator from activating;
b) activating a self test by creating a current imbalance, which occurs across at least two different half cycles of opposite polarity;
c) testing a fault circuit by reading said current imbalance.

### Claim at position 33

72-74. (canceled)

### Claim 75

A method for testing a fault circuit comprising:
periodically outputting a circuit hinder signal to hinder a disconnect signal from a fault detector circuit, the circuit hinder signal being output at a first period of time;
outputting a test signal to said fault detector circuit only if the circuit hinder signal is output, the test signal testing said fault detector circuit;
receiving from said fault detector circuit an output signal in response to the test signal when said fault detector is operative; and
activating an alarm during a second period of time if the output signal is not received during said first period of time.

### Claim at position 35

76-77. (canceled)