# US 2014/0197847 A1 · Resistive memory element sensing using averaging

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- Number: US 2014/0197847 A1
- Document ID: US20140197847A1
- Status: Published application
- Kind: A1
- Application number: 14/221,719
- Filed: 2014-03-21
- Published: 2014-07-17
- Earliest claimed: 2001-08-27
- Assignees: Micrcn Technology, Inc.
- Applicants: Micrcn Technology, Inc.
- Inventors: R. Jacob Baker
- Web page: https://patentgrep.com/patent/US20140197847A1

## CPC

- G01R 27/02: Measuring real or complex resistance, reactance, impedance, or other two-pole characteristics derived therefrom, e.g. time constant (by measuring phase angle only G01R25/00)
- G11C 11/16: using elements in which the storage effect is based on magnetic spin effect
- G11C 11/1659: {Cell access}
- G11C 11/1673: {Reading or sensing circuits or methods}
- G11C 13/004: {Reading or sensing circuits or methods}
- G11C 13/0061: {Timing circuits or methods}
- G11C 2013/0054: {Read is performed on a reference element, e.g. cell, and the reference sensed value is used to compare the sensed value of the selected cell}
- G01R: MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES (indicating correct tuning of resonant circuits H03J3/12)
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

A system for determining the logic state of a resistive memory cell element, for example an MRAM resistive cell element. The system includes a controlled voltage supply, an electronic charge reservoir, a current source, and a pulse counter. The controlled voltage supply is connected to the resistive memory cell element to maintain a constant voltage across the resistive element. The charge reservoir is connected to the voltage supply to provide a current through the resistive element. The current source is connected to the charge reservoir to repeatedly supply a pulse of current to recharge the reservoir upon depletion of electronic charge from the reservoir, and the pulse counter provides a count of the number of pulses supplied by the current source over a predetermined time. The count represents a logic state of the memory cell element.

## Claims

### Claim at position 1

1-27. (canceled)

### Claim 28

A method of measuring a resistance in a circuit, comprising:
maintaining a substantially constant voltage across the circuit;
repeatedly charging and discharging a capacitance through the circuit;
determining a value of the time-average current into the capacitance in response to repeatedly charging and discharging the capacitance during a set time period; and
determining the resistance in the circuit based on the value of the time-average current.

### Claim 29 (depends on 28)

The method of claim 28, wherein repeatedly charging and discharging the capacitance comprises the act of sensing the charge remaining on the capacitance while discharging the capacitance.

### Claim 30 (depends on 29)

The method of claim 29, wherein the act of repeatedly charging and discharging the capacitance comprises recharging the capacitance with a recharging pulse each time the capacitance voltage drops to a predetermined value.

### Claim 31 (depends on 30)

The method of claim 30, wherein the act of determining the value of the time-average current comprises determining a duty cycle of the recharging pulses.

### Claim 32

A resistance measuring circuit, comprising:
a resistance coupled between a row line and a column line of a memory cell array;
a capacitance having first and second nodes;
an operational amplifier having negative feedback to maintain a constant voltage across the resistance when the capacitance is discharged;
a first transistor to provide a recharging pulse to the capacitance when a voltage across the first and second nodes is less than a reference voltage;
a second transistor to enable the capacitance to be discharged through the resistance when the voltage across the first and second nodes is greater than the reference voltage; and
circuitry to determine a time average current into the capacitance based on a duty cycle of the recharging pulses.

### Claim 33 (depends on 32)

The resistance measuring circuit of claim 32, further comprising circuitry to determine a value of the resistance based on the time average current and the constant voltage.

### Claim 34

A resistance measuring circuit, comprising:
a resistance coupled between a row line and a column line of a memory cell array;
a capacitance having first and second nodes;
an operational amplifier having negative feedback to maintain a constant voltage across the resistance when the capacitance is discharged;
a first access device to provide a recharging pulse to the capacitance when a voltage across the first and second nodes of the capacitance is less than a reference voltage;
a second access device to enable the capacitance to be discharged through the resistance when the voltage across the first and second nodes of the capacitance is greater than the reference voltage; and
circuitry to count the recharging pulses for a period of time and to determine a logical state indicated by the count.

### Claim 35 (depends on 34)

The resistance measuring circuit of claim 34, wherein the count indicates a first logical state if the count is greater than a reference count, and wherein the count indicates a second logical state if the count is less than the reference count.

### Claim 36 (depends on 34)

The resistance measuring circuit of claim 34, wherein the first access device comprises a transistor.

### Claim 37 (depends on 34)

The resistance measuring circuit of claim 34, wherein the second access device comprises a transistor.