# US 2014/0197814 A1 · Programmable frequency range for boost converter clocks > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2014/0197814 A1 - Document ID: US20140197814A1 - Status: Published application - Kind: A1 - Application number: 13/740,062 - Filed: 2013-01-11 - Published: 2014-07-17 - Earliest claimed: 2013-01-11 - Assignees: QUALCOMM Incorporated - Applicants: Qualcomm Incorporated - Inventors: Song S. Shi; Pengfei Li; Lennart Karl-Axel Mathe; Yunfei Shi - Web page: https://patentgrep.com/patent/US20140197814A1 ## CPC - G05F 3/02: Regulating voltage or current - H02M 1/0045: {Converters combining the concepts of switch-mode regulation and linear regulation, e.g. linear pre-regulator to switching converter, linear and switching converter in parallel, same converter or same transistor operating either in linear or switching mode} - H02M 3/155: using semiconductor devices only - H03F 1/0238: {using supply converters} - H02M 1/008: {Plural converter units for generating at two or more independent and non-parallel outputs, e.g. systems with plural point of load switching regulators} - H02M 3/1582: {Buck-boost converters (H02M3/1584 takes precedence)} - G05F: SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES - H02M: APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF (transformers H01F; dynamo-electric converters H02K47/00; controlling transformers, reactors or choke coils, control or regulation of electric motors, generators or dynamo-electric converters H02P) - H03F: AMPLIFIERS ## Abstract Techniques for generating a boost clock signal for a boost converter from a buck converter clock signal, wherein the boost clock signal has a limited frequency range. In an aspect, the boost clock signal has a maximum frequency determined by Vbst/T, wherein Vbst represents the difference between a target output voltage and a battery voltage, and T represents a predetermined cycle duration. The boost converter may include a pulse insertion block to limit the minimum frequency of the boost clock signal, and a dynamic blanking/delay block to limit the maximum frequency of the boost clock signal. Further techniques are disclosed for generally implementing the minimum frequency limiting and maximum frequency limiting blocks. ## Claims ### Claim 1 An apparatus comprising: a switched-mode power supply configured to generate a target output voltage, the power supply comprising: a first switch coupled to an inductor, the first switch configurable to be selectively closed or opened; and a control block configured to generate a control signal from a buck clock signal to configure the first switch to be selectively closed or opened, wherein the control block is configured to limit a switching frequency of the control signal to a range defined by a minimum frequency and a maximum frequency. ### Claim 2 (depends on 1) The apparatus of claim 1, the first switch comprising an NMOS transistor, wherein selectively closing or opening the switch corresponds to coupling or decoupling the inductor to ground via the NMOS transistor. ### Claim 3 (depends on 1) The apparatus of claim 1, the maximum frequency configured to increase as the target output voltage is increased. ### Claim 4 (depends on 3) The apparatus of claim 3, the power supply coupled to a battery voltage, wherein a boost voltage is defined as the difference between the target output voltage and the battery voltage, and wherein the maximum frequency is directly proportional to the boost voltage. ### Claim 5 (depends on 1) The apparatus of claim 1, the control block comprising a pulse insertion block configured to insert pulses in the buck clock signal to generate the control signal. ### Claim 6 (depends on 2) The apparatus of claim 2, the power supply further comprising a second switch coupled to the inductor, the second switch comprising a PMOS transistor configured to selectively couple or decouple the inductor to an output node configured to support the target output voltage. ### Claim 7 (depends on 6) The apparatus of claim 6, the control signal coupled to the NMOS transistor to turn the NMOS transistor on or off, the control block further configured to generate a second control signal derived from the control signal coupled to the PMOS transistor to turn the PMOS transistor on or off. ### Claim 8 (depends on 7) The apparatus of claim 7, the control block configured to turn the PMOS transistor on when the NMOS transistor is off, and to turn the PMOS transistor off when the NMOS transistor is on. ### Claim 9 (depends on 2) The apparatus of claim 2, the control block comprising a Force_Noff generation circuit configured to force the NMOS transistor off during a predetermined period of time. ### Claim 10 (depends on 9) The apparatus of claim 9, the Force_Noff generation circuit comprising: a logic block configured to accept the buck clock signal, the logic block generating an output corresponding to the control signal; an inverting buffer coupled to the output of the logic block; a D-Q flip-flop comprising a clock input coupled to the output of the inverting buffer, the D input of the flip-flop coupled to a 1 input; a dynamic delay block coupled to the Q output of the flip-flop; an AND gate comprising a first input coupled to the Q output of the flip-flop and a second input coupled to an inverse of the output of the dynamic delay block, the output of the AND gate coupled to the logic block. ### Claim 11 A method comprising: generating a target output voltage using a switched-mode power supply comprising a first switch coupled to an inductor; generating a control signal from a buck clock signal to selectively close or open the first switch; and limiting the switching frequency of the control signal to a range defined by a minimum frequency and a maximum frequency. ### Claim 12 (depends on 11) The method of claim 11, further comprising: increasing the maximum frequency in response to the target output voltage being increased. ### Claim 13 (depends on 12) The method of claim 12, wherein a boost voltage is defined as the difference between the target output voltage and a battery voltage coupled to the switched-mode power supply, and wherein the maximum frequency is directly proportional to the boost voltage. ### Claim 14 (depends on 11) The method of claim 11, further comprising inserting pulses in the buck clock signal to generate the control signal. ### Claim 15 (depends on 11) The method of claim 11, further comprising swallowing pulses in the buck clock signal to generate the control signal. ### Claim 16 An apparatus comprising: means for generating a target output voltage using a switched-mode power supply comprising a first switch coupled to an inductor; means for generating a control signal from a buck clock signal to selectively close or open the first switch; and means for limiting the switching frequency of the control signal to a range defined by a minimum frequency and a maximum frequency. ### Claim 17 (depends on 16) The apparatus of claim 16, further comprising: means for increasing the maximum frequency in response to the target output voltage being increased. ### Claim 18 (depends on 17) The apparatus of claim 17, wherein a boost voltage is defined as the difference between the target output voltage and a battery voltage coupled to the switched-mode power supply, and wherein the maximum frequency is directly proportional to the boost voltage. ### Claim 19 (depends on 16) The apparatus of claim 16, further comprising inserting pulses in the buck clock signal to generate the control signal. ### Claim 20 (depends on 16) The apparatus of claim 16, further comprising swallowing pulses in the buck clock signal to generate the control signal.