# US 2014/0197752 A1 · Current driver for an array of led diodes

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- Number: US 2014/0197752 A1
- Document ID: US20140197752A1
- Status: Published application
- Kind: A1
- Application number: 14/154,573
- Filed: 2014-01-14
- Published: 2014-07-17
- Earliest claimed: 2013-01-17
- Assignees: STMicroelectronics S.r.l.
- Applicants: STMicroelectronics S.r.l.
- Inventors: Salvatore Pantano; Marco Martini
- Web page: https://patentgrep.com/patent/US20140197752A1

## CPC

- H05B 45/14: using electrical feedback from LEDs or from LED modules
- H05B 45/46: having LEDs disposed in parallel lines
- H05B: ELECTRIC HEATING; ELECTRIC LIGHT SOURCES NOT OTHERWISE PROVIDED FOR; CIRCUIT ARRANGEMENTS FOR ELECTRIC LIGHT SOURCES, IN GENERAL

## Abstract

An array of LED diodes includes N channels each having LEDs coupled in series with a switch. A current driver for the array includes a processing circuit configured to detect N currents flowing respectively through the N channels of the array. The detected currents are converted by a single analog to digital converter, one at a time, into a digital word. The circuit further includes N comparator devices configured to control the N switches as result of a comparison between the digital words and respective target digital words. A memory is provided for storing the digital words received from the analog to digital converter.

## Claims

### Claim 1

A current driver device for an array of LED diodes, the array including N channels each one comprising a plurality of LED diodes and a switch arranged in the electric path between the plurality of LED diodes and a common voltage reference, the current driver comprising:
a processing circuit configured to detect N currents flowing respectively through the N channels of said array of LED diodes and convert each detected current into a digital word,
N comparator devices configured to control said N switches as result of a comparison between said digital words and respective target digital words,
wherein said processing circuit comprises one analog to digital converter configured to convert one at a time the N detected currents into said digital words, and
wherein said processing circuit further comprises a memory configured to store said digital words received from the analog to digital converter.

### Claim 2 (depends on 1)

The current driver according to claim 1, wherein said processing circuit further comprises:
a multiplexer configured to send each of the N detected currents, one at the time, to the analog to digital converter, and
a first counter configured to set the multiplexer to send all the N detected currents, one at the time, to the analog to digital converter.

### Claim 3 (depends on 2)

The current driver according to claim 2, wherein said memory comprises at least N banks each configured to store one of the digital and wherein said processing circuit further comprises:
a demultiplexer configured to send to said memory the digital words received from the analog to digital converter, said first counter configured to set the demultiplexer to address each digital word received from the analog to digital converter towards the respective bank of the memory.

### Claim 4 (depends on 2)

The current driver according to claim 2, wherein the analog to digital converter is configured to send an end-of-conversion signal to the first counter as a starting signal for the count of first counter.

### Claim 5 (depends on 1)

The current driver according to claim 1, wherein each of said comparator devices comprises:
a second counter, and
a comparator configured to compare one digital word stored in the memory and the respective target digital word, said comparator configured to set an up counting or a down counting process of the second counter if respectively the digital word is lesser or greater than the respective target digital word and to stop the counting process of the second counter if the digital word is equal to the respective target digital word, the output digital signal of the second counter controlling the respective switch of the respective channel of the array for increasing or decreasing the channel current value respectively if the digital word is lesser or greater than the target digital word.

### Claim 6 (depends on 5)

The current driver according to claim 5, wherein each one of said switches comprises K transistors arranged in parallel, said second counter being configured to output a digital signal of at least K bits for driving the switch so that each one of the K transistors is respectively driven by at least one bit of said digital signal.

### Claim 7 (depends on 6)

The current driver according to claim 6, wherein said transistors are configured to have same length and different width, so that each one of the K bit of said digital signal has a different weight on the modulation of the current flow of each channel.

### Claim 8 (depends on 5)

The current driver according to claim 5, wherein said comparator is an hysteresis comparator.

### Claim 9 (depends on 5)

The current driver according to claim 5, wherein said second counter is synchronized with a clock signal, which is the result of a digital AND operation between the end-of-conversion signal deriving from the analog to digital converter and a driving signal deriving from said first counter.

### Claim 10 (depends on 6)

The current driver according to claim 6, wherein said second counter is configured for outputting said digital signal if enabled by a status signal indicating the on or off state of the LED diodes of the array.

### Claim 11 (depends on 1)

The current driver according to claim 1, wherein said processing circuit comprises a sample and hold circuit configured to sample all the N detected currents and to send each one of the sampled currents, one at the time, to the analog to digital converter, said sample and hold circuit being enabled to provide the sampled currents to the analog to digital converter if enabled by a status signal indicating the on or off state of the LED diodes of the array.

### Claim 12

A current driving method for an array of LED diodes, the array including N channels each one comprising a plurality of LED diodes and a switch arranged in the electric path between the plurality of LED diodes and a common voltage reference, the method comprising:
detecting N currents flowing through the N current channels of said array,
converting one at a time the N detected currents into digital words,
storing said digital words,
comparing each stored digital word with a respective target digital word,
controlling N switches in response to the comparison between said digital words and respective target digital words.

### Claim 13 (depends on 12)

The method according to claim 12, wherein controlling comprises:
increasing or decreasing a respective channel current value if the digital word is lesser or greater, respectively, than the target digital word.

### Claim 14

A circuit, comprising:
a first load circuit;
a second load circuit;
a first drive transistor coupled in series with the first load circuit;
a second drive transistor coupled in series with the second load circuit;
a first current sensing circuit configured to sense a first current flowing through the first load circuit;
a second current sensing circuit configured to sense a second current flowing through the second load circuit;
a single analog to digital converter circuit;
a multiplexer circuit configured to select one at a time the sensed first and second currents for conversion by said single analog to digital converter to generate first and second digital signals;
a first comparator circuit having an output coupled to control said first drive transistor;
a second comparator circuit having an output coupled to control said second drive transistor;
a demultiplexer circuit configured to pass said first digital signal towards said first comparator and pass said second digital signal towards said second comparator.

### Claim 15 (depends on 14)

The circuit of claim 14, further comprising a memory circuit coupled between the demultiplexer circuit and the first and second comparators and configured to store said first and second digital signals before application to respective first inputs of the first and second comparator circuits.

### Claim 16

The circuit of 15, wherein said first and second comparator circuits each include second inputs configured to receive a threshold value.

### Claim 17 (depends on 14)

The circuit of claim 14, further comprising a counter configured to control selection by said multiplexer circuit.

### Claim 18 (depends on 14)

The circuit of claim 14, further comprising a counter configured to control selection by said demultiplexer circuit, said counter controlled by an end of conversion signal output by said analog to digital converter.