# US 2014/0197552 A1 · Chip arrangement, a method for manufacturing a chip arrangement, integrated circuits and a method for manufacturing an integrated circuit > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2014/0197552 A1 - Document ID: US20140197552A1 - Status: Published application - Kind: A1 - Application number: 13/742,456 - Filed: 2013-01-16 - Published: 2014-07-17 - Earliest claimed: 2013-01-16 - Assignees: Infineon Technologies AG - Applicants: Infineon Technologies AG - Inventors: Ralf Otremba; Josef Hoeglauer; Juergen Schredl; Xaver Schloegel; Wolfram Hable; Manfred Mengel; Joachim Mahler; Khalil Hosseini; Franz-Peter Kalz - Web page: https://patentgrep.com/patent/US20140197552A1 ## CPC - H10W 74/40: characterised by their materials - H10W 40/10: Arrangements for heating - H10W 70/481: {for devices being provided for in groups H10D8/00 - H10D48/00} - H10W 74/01: Manufacture or treatment - H10W 74/111: {the semiconductor body being completely enclosed} - H10W 76/17: characterised by their materials - H10W 90/811: {Multiple chips on leadframes} - H10W 72/884: {Die-attach connectors and bond wires} - H10W 90/736: {between a chip and a stacked lead frame, conducting package substrate or heat sink} - H10W 90/756: {between a chip and a stacked lead frame, conducting package substrate or heat sink} - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract A chip arrangement is provided, the chip arrangement, including a carrier; at least one chip electrically connected to a carrier top side; an encapsulation material at least partially surrounding the at least one chip and the carrier top side, wherein the encapsulation material is formed on one or more lateral sides of the carrier; and a ceramic material disposed on a carrier bottom side, and on at least one side of the encapsulation material. ## Claims ### Claim 1 A chip arrangement, comprising: a carrier; at least one chip electrically connected to a carrier top side; an encapsulation material at least partially surrounding the at least one chip and the carrier top side, wherein the encapsulation material is formed on one or more lateral sides of the carrier; and a ceramic material disposed on a carrier bottom side, and on at least one side of the encapsulation material. ### Claim 2 (depends on 1) The chip arrangement according to claim 1, wherein the ceramic material has a coefficient of thermal expansion different from the encapsulation material. ### Claim 3 (depends on 1) The chip arrangement according to claim 1, wherein the ceramic material comprises ceramic particles embedded in a polymer material. ### Claim 4 (depends on 1) The chip arrangement according to claim 1, wherein the ceramic material comprises a laminate sheet comprising an embedding portion and a filler portion; wherein the embedding portion comprises at least one material from the following group of materials, the group of materials consisting of: epoxy, polyimide, thermoset, thermoplast, silicone, polyacrylate or mixtures thereof; and wherein the filler portion comprises one or more structures comprising at least one material from the following group of materials, the group of materials consisting of: calcium oxide, aluminum oxide, silicon oxide, aluminum nitride, and zirconium oxide, boron nitride, a metal oxide, a metal nitride, a metal carbide, a metal boron. ### Claim 5 (depends on 4) The chip arrangement according to claim 4, wherein the one or more structures comprises at least one from the following group of structures, the group consisting of: particles, nanoparticles, microparticles, fibers, microfibers, nanofibers, nanostructures, microstructures. ### Claim 6 (depends on 1) The chip arrangement according to claim 1, wherein the ceramic material is disposed on at least one side of the encapsulation material, wherein the at least one side of the encapsulation material is substantially level with and abuts the carrier bottom side. ### Claim 7 (depends on 1) The chip arrangement according to claim 1, wherein the at least one chip comprises at least one of a power semiconductor chip, a semiconductor logic chip and a semiconductor memory chip. ### Claim 8 (depends on 7) The chip arrangement according to claim 7, wherein the power semiconductor chip comprises at least one power semiconductor device from the group consisting of: a power transistor, a power MOS transistor, a power bipolar transistor, a power field effect transistor, a power insulated gate bipolar transistor, a thyristor, a MOS controlled thyristors, a silicon controlled rectifier, a power schottky diode, a silicon carbide diode, a gallium nitride device. ### Claim 9 (depends on 7) The chip arrangement according to claim 7, wherein the semiconductor logic chip comprises at least one semiconductor logic device from the group consisting of: an application specific integrated circuit, a driver, a controller, a sensor. ### Claim 10 (depends on 1) The chip arrangement according to claim 1, wherein the encapsulation material comprises at least one from the following group of materials, the group consisting of: filled or unfilled epoxy, pre-impregnated composite fibers, reinforced fibers, laminate, a mold material, a thermoset material, a thermoplastic material, filler particles, fiber-reinforced laminate, fiber-reinforced polymer laminate, fiber-reinforced polymer laminate with filler particles. ### Claim 11 (depends on 1) The chip arrangement according to claim 1, wherein the carrier comprises a lead frame, the lead frame comprising at least one from the following group of materials, the group of materials consisting of: copper, nickel, iron, copper alloy, nickel alloy, iron alloy. ### Claim 12 A method for manufacturing a chip arrangement, the method comprising: electrically connecting at least one chip to a carrier top side; at least partially surrounding the at least one chip and the carrier top side with an encapsulation material, wherein the encapsulation material is formed on one or more lateral sides of the carrier; disposing a ceramic material on a carrier bottom side, and on at least one side of the encapsulation material. ### Claim 13 An integrated circuit, comprising: a chip; encapsulation material at least partially covering the chip; a layer stack disposed at least partially over the encapsulation material, the layer stack comprising: a polymer layer disposed over the encapsulation material; and a metal layer or a ceramic layer disposed over the polymer layer. ### Claim 14 (depends on 13) The integrated circuit of claim 13, wherein the polymer layer has a thickness ranging from about 200 μm to about 500 μm. ### Claim 15 (depends on 13) The integrated circuit of claim 13, wherein the polymer layer comprises at least one material from the following group of materials, the group of materials consisting of: polyimide, epoxy, acrylate, silicone, Polyethylene terephthalate, Polyphenylensulfide, Polyetherimide, Polysulfone, Liquid Crystalline Polymers, Polyamideimide and Polyphenyloxide. ### Claim 16 (depends on 13) The integrated circuit of claim 13, wherein the polymer layer is different from the encapsulation material. ### Claim 17 (depends on 13) The integrated circuit of claim 13, wherein the polymer layer has a different coefficient of thermal expansion from the encapsulation material. ### Claim 17 (depends on 13) The integrated circuit of claim 13, wherein the ceramic layer comprises a low temperature co-fired ceramic. ### Claim 18 (depends on 13) The integrated circuit of claim 13, wherein the ceramic layer comprises at least one from the following group of materials, the group of materials consisting of: calcium oxide, aluminum oxide, silicon oxide, aluminum nitride, and zirconium oxide, boron nitride, a metal oxide, a metal nitride, a metal carbide, a metal boron. ### Claim 19 (depends on 13) The integrated circuit of claim 13, wherein the ceramic material comprises ceramic particles embedded in a polymer material. ### Claim 20 An integrated circuit, comprising: a carrier; a chip mounted on the carrier; encapsulation material at least partially covering the chip and the carrier; a layer stack disposed over the carrier on a side of the carrier opposite the chip, the layer stack comprising: a polymer layer disposed over the carrier; and a metal layer or a ceramic layer disposed over the polymer layer. ### Claim 21 (depends on 20) The integrated circuit of claim 20, wherein the polymer layer is different from the encapsulation material. ### Claim 22 (depends on 20) The integrated circuit of claim 20, wherein the polymer layer has a different coefficient of thermal expansion from the encapsulation material. ### Claim 23 (depends on 20) The integrated circuit of claim 20, wherein the ceramic layer comprises a low temperature co-fired ceramic. ### Claim 24 (depends on 20) The integrated circuit of claim 20, wherein the ceramic material comprises ceramic particles embedded in a polymer material. ### Claim 25 A method for manufacturing an integrated circuit, the method comprising: at least partially covering a chip with encapsulation material; disposing a layer stack at least partially over the encapsulation material, the layer stack comprising: a polymer layer disposed over the encapsulation material; and a metal layer or a ceramic layer disposed over the polymer layer.