# US 2014/0197551 A1 · Method for Fabricating a Semiconductor Chip Panel > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2014/0197551 A1 - Document ID: US20140197551A1 - Status: Published application - Kind: A1 - Application number: 13/741,113 - Filed: 2013-01-14 - Published: 2014-07-17 - Earliest claimed: 2013-01-14 - Assignees: Infineon Technologies AG - Applicants: Infineon Technologies AG - Inventors: Daniel Porwol; Edward Fuergut - Web page: https://patentgrep.com/patent/US20140197551A1 ## CPC - H10W 74/017: {Auxiliary layers for moulds, e.g. release layers or layers preventing residue} - H10W 72/0198: {batch processes} - H10W 74/00: Encapsulations, e.g. protective coatings - H10W 74/01: Manufacture or treatment - H10W 74/014: {using batch processing} - H10W 74/019: {using temporary auxiliary substrates (H10W74/017 takes precedence)} - H10W 70/099: {Connecting interconnections to insulating or insulated package substrates, interposers or redistribution layers} - H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40) - H10W 72/073: {of die-attach connectors} - H10W 72/874: {On different surfaces} - H10W 72/9413: {on encapsulations} - H10W 74/111: {the semiconductor body being completely enclosed} - H10W 74/114: {by a substrate and the encapsulations} - H10W 90/10: Configurations of laterally-adjacent chips - H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL} - H10W 90/736: {between a chip and a stacked lead frame, conducting package substrate or heat sink} - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract The method comprises providing a carrier, providing a plurality of semiconductor chips, the semiconductor chips each comprising a first main face and a second main face opposite to the first main face and side faces connecting the first and second main faces, placing the semiconductor chips on the carrier with the second main faces facing the carrier, and applying an encapsulation material to the side faces of the semiconductor chips. ## Claims ### Claim 1 A method for fabricating a semiconductor chip panel, the method comprising: providing a carrier; providing a plurality of semiconductor chips, the semiconductor chips each comprising a first main face and a second main face opposite to the first main face and side faces connecting the first and second main faces; placing the semiconductor chips on the carrier with the second main faces facing the carrier; and applying an encapsulation material to the side faces of the semiconductor chips. ### Claim 2 (depends on 1) The method according to claim 1, further comprising, before applying the encapsulation material covering the first main faces of the semiconductor chips so that the encapsulation material will not be applied to the first main faces. ### Claim 3 (depends on 2) The method according to claim 2, wherein the first main faces are covered by a polymer film or a polymer foil. ### Claim 4 (depends on 1) The method according to claim 1, wherein applying the encapsulation material comprises transfer molding. ### Claim 5 (depends on 1) The method according to claim 1, wherein at least some of the semiconductor chips comprise one or more of a power transistor, a vertical transistor, an MOS transistor, an insulated gate bipolar transistor, a logic circuit, a sensor, and a passive component. ### Claim 6 (depends on 1) The method according to claim 1, wherein the semiconductor chips are similar or identical and are placed on the carrier with similar or different spatial orientation. ### Claim 7 (depends on 1) The method according to claim 1, wherein the semiconductor chips comprise different electrical devices. ### Claim 8 (depends on 1) The method according to claim 1, wherein at least some of the semiconductor chips comprise a thickness in a range from 5 μm-1000 μm, in particular from 30 μm-80 μm. ### Claim 9 (depends on 1) The method according to claim 1, wherein all of the semiconductor chips have an equal thickness. ### Claim 10 (depends on 1) The method according to claim 1 wherein the semiconductor chips comprise different thickness. ### Claim 11 (depends on 1) The method according to claim 1, wherein the encapsulation material comprises one or more of an insulating material, a mold material, a polymer material, a polyimide material, a resin material, an epoxy resin material, a silicone material, a ceramic material, and a glass material. ### Claim 12 A semiconductor chip package, comprising: a semiconductor chip comprising a first main face and a second main face opposite to the first main face and side faces connecting the first and second main faces; and an encapsulation material covering the side faces of the semiconductor chip, wherein the encapsulation material is not applied on the first and second main faces. ### Claim 13 (depends on 12) The semiconductor chip package according to claim 12, wherein the semiconductor chip comprises one or more of a power transistor, a vertical transistor, an MOS transistor, an insulated gate bipolar transistor, a logic circuit, a sensor, a flyback diode, and a passive component. ### Claim 14 (depends on 12) The semiconductor chip package according to claim 12, wherein the semiconductor chip comprises a thickness in a range from 30 μm-80 μm. ### Claim 15 (depends on 12) The semiconductor chip package according to claim 12, wherein the encapsulation material comprises one or more of an insulating material, a mold material, a polymer material, a polyimide material, a resin material, an epoxy resin material, a silicon material, a ceramic material, and a glass material. ### Claim 16 (depends on 12) The semiconductor chip package according to claim 12, wherein the encapsulation material covers the first and/or second main faces on an edge portion. ### Claim 17 A semiconductor chip package, comprising: a semiconductor chip module comprising two or more semiconductor chips, wherein at least one of the semiconductor chips comprises a first main face and a second main face opposite to the first main face and side faces connecting the first and second main faces; and an encapsulation material covering the side faces of the at least one semiconductor chip. ### Claim 18 (depends on 17) The semiconductor chip package according to claim 17, wherein the encapsulation material is not applied on the first and second main faces of the at least one semiconductor chip. ### Claim 19 (depends on 17) The semiconductor chip package according to claim 17, wherein the at least one semiconductor chip comprises one or more of a power transistor, a vertical transistor, an MOS transistor, an insulated gate bipolar transistor, a logic circuit, a sensor, and a passive component. ### Claim 20 (depends on 17) The semiconductor chip package according to claim 17, further comprising a ring-like portion of the encapsulation material extending from the side faces and projecting beyond a plane of one of the first or second main faces.