# US 2014/0197549 A1 · Semiconductor package and method of manufacturing the same > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2014/0197549 A1 - Document ID: US20140197549A1 - Status: Published application - Kind: A1 - Application number: 14/154,390 - Filed: 2014-01-14 - Published: 2014-07-17 - Earliest claimed: 2013-01-14 - Assignees: Samsung Electronics Co., Ltd. - Applicants: Samsung Electronics Co., Ltd. - Inventors: Seok-Won JEONG - Web page: https://patentgrep.com/patent/US20140197549A1 ## CPC - H10W 74/111: {the semiconductor body being completely enclosed} - H10W 42/00: Arrangements for protection of devices (arrangements for thermal protection H10W40/00) - H10W 76/40: Fillings or auxiliary members in containers, e.g. centering rings (fillings or auxiliary members for thermal protection or control in containers or encapsulations H10W40/70) - H10W 72/0198: {batch processes} - H10W 72/5522: {comprising gold [Au]} - H10W 72/5524: {comprising aluminium [Al]} - H10W 72/884: {Die-attach connectors and bond wires} - H10W 74/00: Encapsulations, e.g. protective coatings - H10W 74/117: {the substrate having spherical bumps for external connection} - H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL} - H10W 90/754: {between a chip and a stacked insulating package substrate, interposer or RDL} - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract A semiconductor package includes a package substrate, a semiconductor chip, a die attach film, a molding member, and a dummy finger. A bond finger is arranged on an upper surface of the package substrate. The semiconductor chip is arranged on the upper surface of the package substrate, and electrically connected to the bond finger. The die attach film is interposed between the semiconductor chip and the package substrate such that the semiconductor chip is attached to the package substrate. The molding member is formed on the upper surface of the package substrate to cover the semiconductor chip. The dummy finger is formed between the upper surface of the package substrate and the molding member. Moisture in the void formed in the die attach film may be released through the discharge passageway. Thus, the package substrate is prevented from being swollen during a subsequent thermal process such as a reflow process. ## Claims ### Claim 1 A semiconductor package comprising: a package substrate including at least one bond finger; a semiconductor chip on the upper surface of the package substrate, the semiconductor chip electrically connected to the bond finger; a die attach film between the semiconductor chip and the package substrate, the die attach film attaching the semiconductor chip to the package substrate; a molding member on the upper surface of the package substrate, the molding member covering the semiconductor chip; and at least one dummy finger between the upper surface of the package substrate and the molding member. ### Claim 2 (depends on 1) The semiconductor package of claim 1, wherein the at least one dummy finger and the molding member are configured to not closely adhere to each other such that at least one discharge passageway is formed therebetween. ### Claim 3 (depends on 2) The semiconductor package of claim 2, wherein the at least one dummy finger extends from the die attach film to an outer surface of the molding member, and the at least one discharge passageway is exposed through the outer surface of the molding member. ### Claim 4 (depends on 2) The semiconductor package of claim 2, wherein the at least one discharge passageway extends between the die attach film and an outer surface of the molding member, and one end of the at least one discharge passageway is enclosed by the molding member. ### Claim 5 (depends on 1) The semiconductor package of claim 1, wherein the at least one dummy finger includes a metal. ### Claim 6 (depends on 1) The semiconductor package of claim 1, wherein the at least one dummy finger and the at least one bond finger includes substantially a same material. ### Claim 7 (depends on 1) The semiconductor package of claim 1, further comprising: a conductive wire configured to electrically connect the semiconductor chip to the at least one bond finger. ### Claim 8 (depends on 1) The semiconductor package of claim 1, further comprising: an external terminal on a lower surface of the package substrate. ### Claim 9 A method of manufacturing a semiconductor package, the method comprising: forming at least one bond finger on an upper surface of a package substrate; forming at least one dummy finger on the upper surface of the package substrate; attaching a semiconductor chip to the upper surface of the package substrate using a die attach film; electrically connecting the semiconductor chip with the at least one bond finger; and forming a molding member on the upper surface of the package substrate to cover the semiconductor chip and the at least one dummy finger, wherein the at least one dummy finger includes a material that does not closely adhere to the molding member to format least one first discharge passageway between the at least one dummy finger and the molding member. ### Claim 10 (depends on 9) The method of claim 9, further comprising performing a heat process to release air or moisture in a void, which is formed in the die attach film, through the at least one first discharge passageway. ### Claim 11 (depends on 10) The method of claim 10, wherein forming the molding member includes: arranging a plurality of the package substrates on a substrate frame; forming the molding member on the package substrates; and separating the substrate frame into individual package substrates, wherein the at least one first discharge passageway of each of the individual package substrate is exposed through an outer surface of the molding member. ### Claim 12 (depends on 10) The method of claim 10, wherein forming the molding member includes: arranging a plurality of the package substrates on a substrate frame, the substrate frame having at least one second discharge passageway, the at least one second passageway in communication with the at least one first discharge passageway; forming the molding member on the package substrates with releasing the air or the moisture in the void through the at least one first discharge passageway and the at least one second discharge passageway; separating the substrate frame into individual package substrates; and enclosing the at least one first discharge passageway. ### Claim 13 (depends on 9) The method of claim 9, wherein the at least one bond finger and the at least one dummy finger are formed simultaneously. ### Claim 14 (depends on 13) The method of claim 13, wherein the at least one bond finger and the at least one dummy finger are formed simultaneously by a single plating process. ### Claim 15 (depends on 9) The method of claim 9, further comprising: forming a conductive wire electrically connecting the semiconductor chip to the at least one bond finger. ### Claim 16 A semiconductor package comprising: a package substrate including at least one bond finger; a semiconductor chip on the bond finger, the semiconductor chip electrically connected to the package substrate through the bond finger; a die attach film between the semiconductor chip and the package substrate, the die attach film attaching the semiconductor chip to the package substrate; a molding member on the package substrate; and at least one dummy finger between the package substrate and the molding member and surrounding the die attach film, the at least one dummy finger configured to not closely adhere to the molding member to provide at least one discharge passage between the at least one dummy finger and the molding member. ### Claim 17 (depends on 16) The semiconductor package of claim 16, wherein one end of the at least one discharge passageway is exposed through an outer surface of the molding member. ### Claim 18 (depends on 16) The semiconductor package of claim 16, wherein the at least one discharge passageway facing an outer surface of the molding member is enclosed. ### Claim 19 (depends on 18) The semiconductor package of claim 18, wherein the at least one discharge passageway facing an outer surface of the molding member is enclosed by the molding member. ### Claim 20 (depends on 16) The semiconductor package of claim 16, wherein the at least one dummy finger and the at least one bond finger includes substantially a same material.