# US 2014/0197547 A1 · Package on package structures and methods for forming the same

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- Number: US 2014/0197547 A1
- Document ID: US20140197547A1
- Status: Published application
- Kind: A1
- Application number: 14/212,233
- Filed: 2014-03-14
- Published: 2014-07-17
- Earliest claimed: 2012-03-28
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Company, Ltd.
- Inventors: Jung Wei CHENG; Tsung-Ding WANG; Chien-Hsun LEE; Chun-Chih CHUANG
- Web page: https://patentgrep.com/patent/US20140197547A1

## CPC

- H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts}
- H10W 74/01: Manufacture or treatment
- H10W 74/114: {by a substrate and the encapsulations}
- H10W 74/129: {forming a chip-scale package [CSP]}
- H10W 90/00: Package configurations
- H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40)
- H10W 72/072: {of bump connectors}
- H10W 72/075: {of bond wires}
- H10W 72/241: {Dispositions, e.g. layouts}
- H10W 72/252: {comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu}
- H10W 72/29: Bond pads specially adapted therefor
- H10W 72/59: Bond pads specially adapted therefor
- H10W 72/934: {Cross-sectional shape, i.e. in side view}
- H10W 72/9415: {relative to the surface, e.g. recessed, protruding}
- H10W 72/9445: {Top-view layouts, e.g. mirror arrays}
- H10W 72/952: {comprising metals or metalloids, e.g. PbSn, Ag or Cu}
- H10W 74/00: Encapsulations, e.g. protective coatings
- H10W 74/142: {the encapsulations exposing the passive side of the semiconductor body}
- H10W 74/15: on active surfaces of flip-chip devices, e.g. underfills
- H10W 90/28: the stacked chips having different sizes, e.g. chip stacks having a pyramidal shape
- H10W 90/297: {characterised by the through-semiconductor vias [TSVs] in the stacked chips}
- H10W 90/722: {between stacked chips}
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/754: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A method of forming a semiconductor device package includes removing a portion of a first connector and a molding compound surrounding the first connector to form an opening, wherein the first connector is part of a first package, and removing the portion of the first connector comprises forming a surface on the first connector which is at an angle with respect to a top surface of the molding compound. The method further includes placing a second connector in the opening, wherein the second connector is part of a second package having a semiconductor die. The method further includes bonding the second connector to a remaining portion of the first connector.

## Claims

### Claim 1

A method of forming a semiconductor device package, the method comprising:
removing a portion of a first connector and a molding compound surrounding the first connector to form an opening, wherein the first connector is part of a first package, and removing the portion of the first connector comprises forming a surface on the first connector which is at an angle with respect to a top surface of the molding compound;
placing a second connector in the opening, wherein the second connector is part of a second package having a semiconductor die; and
bonding the second connector to a remaining portion of the first connector.

### Claim 2 (depends on 1)

The method of claim 1, wherein removing the portion of the first connector comprises forming an opening having a depth from the top surface of the molding compound ranging from about 50 microns (μm) to about 250 μm.

### Claim 3 (depends on 1)

The method of claim 1, wherein removing the portion of the first connector comprises forming the angle in a range from about 15° to about 45°.

### Claim 4 (depends on 1)

The method of claim 1, wherein bonding the second connector to the remaining portion of the first connector comprises establishing a distance from a bottom surface of the second package to a top surface of the first package ranging from about 100 μm to about 350 μm.

### Claim 5 (depends on 1)

The method of claim 1, wherein removing the portion of the first connector comprises forming the angle in a range from about 45° to about 90°.

### Claim 6 (depends on 1)

The method of claim 1, wherein removing the portion of the first connector comprises forming a surface in the first connector parallel to the top surface of the molding compound.

### Claim 7 (depends on 1)

The method of claim 1, wherein removing the portion of the first connector comprises forming the opening having a maximum width ranging from about 100 μm to about 300 μm.

### Claim 8 (depends on 1)

The method of claim 1, wherein removing the portion of the first connector comprises removing the portion of the first connector using a blade with a tip having a shape selected from the group consisting of a rectangular shape, a hemispherical shape, a pyramid shape, and a blade-tip shape.

### Claim 9

A semiconductor device package comprising:
a first package comprising:
a first connector;
a second connector spaced from the first connector along a first direction;
a third connector spaced from the first connector along a second direction different from the first direction;
a molding compound between the first connector and the third connector; and
an opening in the molding compound between the first connector and the second connector;
a second package bonded to the first package, wherein the second package comprises:
a bonding element, wherein the bonding element extends into the opening, and the bonding element is bonded to at least the first connector.

### Claim 10 (depends on 9)

The semiconductor device package of claim 9, wherein the molding compound has a curved sidewall.

### Claim 11 (depends on 9)

The semiconductor device package of claim 9, wherein a width of the bonding element is greater than a width of the first connector.

### Claim 12 (depends on 9)

The semiconductor device package of claim 9, wherein a width of the opening is greater than a width of at least one of a top surface of the first connector or a top surface of the second connector.

### Claim 13 (depends on 9)

The semiconductor device package of claim 9, wherein a width of the opening is substantially equal to a width of at least one of a top surface of the first connector or a top surface of the second connector.

### Claim 14 (depends on 9)

The semiconductor device package of claim 9, wherein a distance from a bottom surface of the second package to a top surface of the first package is from about 100 μm to about 350 μm.

### Claim 15 (depends on 9)

The semiconductor device package of claim 9, wherein a distance from a bottom surface of the second package to a top surface of the molding compound is from about 10 μm to about 100 μm.

### Claim 16

A packaged semiconductor device comprising:
a plurality of first conductive structures on a first package with a first semiconductor die;
a plurality of second conductive structures on a second package with a second semiconductor die;
a plurality of bonding structures between the first package and the second package, wherein each bonding structure of the plurality of bonding structures connects a first conductive structure of the plurality of first conductive structures with a corresponding second conductive structure of the plurality of second conductive structure; and
a molding compound having a first curved sidewall adjacent to each first conductive structure of the plurality of first conductive structures.

### Claim 17 (depends on 16)

The packaged semiconductor device of claim 16, wherein the molding compound has a linear sidewall connected to the first curved sidewall.

### Claim 18 (depends on 16)

The packaged semiconductor device of claim 16, wherein the molding compound has a second curved sidewall connected to the first curved sidewall.

### Claim 19 (depends on 16)

The packaged semiconductor device of claim 16, wherein each bonding structure of the plurality of bonding structures comprises a linear sidewall with a length in a range from 50 microns (μm) to about 250 μm.

### Claim 20 (depends on 16)

The packaged semiconductor device of claim 16, wherein a height from a top surface of the molding compound to a top surface of the first semiconductor die ranges from about 50 μm to about 250 μm.