# US 2014/0197545 A1 · Non-cylindrical conducting shapes in multilayer laminated substrate cores

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- Number: US 2014/0197545 A1
- Document ID: US20140197545A1
- Status: Published application
- Kind: A1
- Application number: 13/743,252
- Filed: 2013-01-16
- Published: 2014-07-17
- Earliest claimed: 2013-01-16
- Assignees: Intel Corporation
- Inventors: Harold R. Chase; Mathew J. Manusharow; Mark S. Hlad; Mihir K. Roy
- Web page: https://patentgrep.com/patent/US20140197545A1

## CPC

- H05K 1/165: {incorporating printed inductors}
- H05K 1/0222: {for shielding around a single via or around a group of vias, e.g. coaxial vias or vias surrounded by a grounded via fence}
- H10W 42/20: protecting against electromagnetic or particle radiation, e.g. light, X-rays, gamma-rays or electrons
- H10W 44/501: {Inductive arrangements (H10W44/20 takes precedence)}
- H10W 70/635: {Through-vias}
- H10W 70/685: comprising multiple insulating layers
- H10W 44/212: {Coaxial feed-throughs in substrates}
- H10W 72/877: {Bump connectors and die-attach connectors}
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H05K: PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

Non-cylindrical conducting shapes are described in the context of multilayer laminated substrate cores. In one example a package substrate core includes a plurality of dielectric layers pressed together to form a multilayer core, a conductive bottom pattern on a bottom surface of the multilayer core, and a conductive top pattern on a top surface of the multilayer core. At least one elongated via extends through each layer of the multilayer core, each elongated via containing a conductor and each connected to a conductor of a via in an adjacent layer to electrically connect the top pattern and the bottom pattern through the conductors of the elongated vias.

## Claims

### Claim 1

A package substrate core comprising:
a plurality of dielectric layers pressed together to form a multilayer core;
a conductive bottom pattern on a bottom surface of the multilayer core;
a conductive top pattern on a top surface of the multilayer core;
at least one elongated via through each layer of the multilayer core, each elongated via containing a conductor and each connected to a conductor of a via in an adjacent layer to electrically connect the top pattern and the bottom pattern through the conductors of the elongated vias.

### Claim 2 (depends on 1)

The package substrate core of claim 1, further comprising at least one conductive path between a first and a second layer of the multilayer core to connect the conductor in the elongated via of the first layer to the conductor in the elongated via of the second layer.

### Claim 3 (depends on 2)

The package substrate core of claim 2, wherein the conductive path is a loop inductor.

### Claim 4 (depends on 1)

The package substrate core of claim 1, wherein the conductive top pattern, the conductive bottom pattern, and a conductor contained in each elongated via is formed of copper.

### Claim 5 (depends on 1)

The package substrate core of claim 1, further comprising a drilled channel proximate an elongated via in at least one layer, the drilled channel being filled with conductive material.

### Claim 6 (depends on 5)

The package substrate core of claim 5, wherein the conductive material is coupled to a voltage to provide an isolation shield for the conductor contained in each elongated via.

### Claim 7 (depends on 5)

The package substrate core of claim 5, wherein the drilled channel is separated from the elongated via by a dielectric.

### Claim 8 (depends on 6)

The package substrate core of claim 6, wherein the via conductor carries data signals.

### Claim 9 (depends on 1)

The package substrate core of claim 1, wherein the via conductor carries power for a die attached to the core.

### Claim 10 (depends on 1)

The package substrate core of claim 1, wherein the elongated vias are formed by drilling.

### Claim at position 11

-15. (canceled)

### Claim 16

A semiconductor device comprising:
a semiconductor die;
a substrate including a multilayer core having a plurality of dielectric layers pressed together, the substrate being attached to the semiconductor die; and
at least one elongated via through each layer of the multilayer core, each elongated via containing a conductor and each elongated via connected to a conductor of a via in an adjacent layer to electrically connect the semiconductor die to a bottom conductive pattern of the core through the conductors of the elongated vias.

### Claim 17 (depends on 16)

The semiconductor device of claim 16, the substrate further comprising loop inductors between layers of the multilayer core.

### Claim 18 (depends on 16)

The semiconductor device of claim 16, further comprising a package cover attached to the substrate and covering the semiconductor die.