# US 2014/0197543 A1 · Enforcement of Semiconductor Structure Regularity for Localized Transistors and Interconnect > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2014/0197543 A1 - Document ID: US20140197543A1 - Status: Published application - Kind: A1 - Application number: 14/216,891 - Filed: 2014-03-17 - Published: 2014-07-17 - Earliest claimed: 2008-01-31 - Assignees: Tela Innovations, Inc. - Applicants: Tela Innovations, Inc. - Inventors: Stephen Kornachuk; Jim Mali; Carole Lambert; Scott T. Becker - Web page: https://patentgrep.com/patent/US20140197543A1 ## CPC - H10W 20/43: Layouts of interconnections - G06F 30/392: Floor-planning or layout, e.g. partitioning or placement - G06F 30/394: Routing (G06F30/396 takes precedence) - G06F 30/3947: global - H10W 20/435: {Cross-sectional shapes or dispositions of interconnections} - H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40) - G06F 2119/18: Manufacturability analysis or optimisation for manufacturability - Y02P 90/02: Total factory control, e.g. smart factories, flexible manufacturing systems [FMS] or integrated manufacturing systems [IMS] - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - Y02P: CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS ## Abstract A global placement grating (GPG) is defined for a chip level to include a set of parallel and evenly spaced virtual lines. At least one virtual line of the GPG is positioned to intersect each contact that interfaces with the chip level. A number of subgratings are defined. Each subgrating is a set of equally spaced virtual lines of the GPG that supports a common layout shape run length thereon. The layout for the chip level is partitioned into subgrating regions. Each subgrating region has any one of the defined subgratings allocated thereto. Layout shapes placed within a given subgrating region in the chip level are placed in accordance with the subgrating allocated to the given subgrating region. Non-standard layout shape spacings at subgrating region boundaries can be mitigated by layout shape stretching, layout shape insertion, and/or subresolution shape insertion, or can be allowed to exist in the final layout. ## Claims ### Claim 1 A semiconductor device, comprising: a first linear-shaped conductive structure defined in a given chip level of the semiconductor device, the first linear-shaped conductive structure having a lengthwise centerline oriented in a first direction, the first linear-shaped conductive structure having a width measured in a second direction perpendicular to the first direction; a second linear-shaped conductive structure defined in the given chip level of the semiconductor device, the second linear-shaped conductive structure having a lengthwise centerline oriented in the first direction, the second linear-shaped conductive structure having a width measured in the second direction; and a third linear-shaped conductive structure defined in the given chip level of the semiconductor device, the third linear-shaped conductive structure having a lengthwise centerline oriented in the first direction, the third linear-shaped conductive structure having a width measured in the second direction, the width of the first linear-shaped conductive structure substantially equal to the width of the third linear-shaped conductive structure, the width of the second linear-shaped conductive structure greater than the width of the first linear-shaped conductive structure, at least a portion of the second linear-shaped conductive structure positioned in a side-by-side manner with at least a portion of the first linear-shaped conductive structure, the side-by-side positioned portions of the first and second linear-shaped conductive structure separated from each other by a first distance as measured in the second direction, and at least a portion of the second linear-shaped conductive structure positioned in a side-by-side manner with at least a portion of the third linear-shaped conductive structure, the side-by-side positioned portions of the second and third linear-shaped conductive structures separated from each other by the first distance as measured in the second direction. ### Claim 2 (depends on 1) The semiconductor device as recited in claim 1, wherein the width of the second linear-shaped conductive structure is an integer multiple of the width of the first linear-shaped conductive structure. ### Claim 3 (depends on 2) The semiconductor device as recited in claim 2, wherein the width of the second linear-shaped conductive structure is substantially equal to two times the width of the first linear-shaped conductive structure. ### Claim 4 (depends on 1) The semiconductor device as recited in claim 1, wherein the width of the first linear-shaped conductive structure is greater than the first distance. ### Claim 5 (depends on 1) The semiconductor device as recited in claim 1, wherein the first linear-shaped conductive structure has a first end and a second end and extends in the first direction from its first end to its second end, wherein the second linear-shaped conductive structure has a first end and a second end and extends in the first direction from its first end to its second end, wherein the third linear-shaped conductive structure has a first end and a second end and extends in the first direction from its first end to its second end, and wherein the first ends of the first, second, and third linear-shaped conductive structures are substantially positioned on a first line oriented in the second direction. ### Claim 6 (depends on 5) The semiconductor device as recited in claim 5, wherein the second ends of the first and second linear-shaped conductive structures are substantially positioned on a second line oriented in the second direction. ### Claim 7 (depends on 6) The semiconductor device as recited in claim 6, wherein a total length of the third linear-shaped conductive structure as measured in the first direction is greater than a total length of the first linear-shaped conductive structure as measured in the first direction. ### Claim 8 (depends on 7) The semiconductor device as recited in claim 7, wherein a total length of the third linear-shaped conductive structure as measured in the first direction is greater than a total length of the second linear-shaped conductive structure as measured in the first direction. ### Claim 9 (depends on 1) The semiconductor device as recited in claim 1, wherein the given chip level is a gate electrode level of the semiconductor device. ### Claim 10 (depends on 1) The semiconductor device as recited in claim 1, further comprising: a substrate, wherein the given chip level is a first interconnect level of the semiconductor device in a direction extending upward from the substrate. ### Claim 11 (depends on 1) The semiconductor device as recited in claim 1, further comprising: a substrate, wherein the given chip level is a second interconnect level of the semiconductor device in a direction extending upward from the substrate. ### Claim 12 (depends on 6) The semiconductor device as recited in claim 6, further comprising: a fourth linear-shaped conductive structure defined in the given chip level of the semiconductor device, the fourth linear-shaped conductive structure having a lengthwise centerline oriented in the first direction, the fourth linear-shaped conductive structure having a width measured in the second direction, the fourth linear-shaped conductive structure positioned in the second direction between the first and second linear-shaped conductive structures. ### Claim 13 (depends on 12) The semiconductor device as recited in claim 12, wherein the lengthwise centerline of the fourth linear-shaped conductive structure is positioned at a midpoint of the first distance as measured in the second direction between the side-by-side positioned portions of the first and second linear-shaped conductive structure. ### Claim 14 (depends on 13) The semiconductor device as recited in claim 13, wherein the width of the fourth linear-shaped conductive structure is substantially equal to the width of the first linear-shaped conductive structure. ### Claim 15 (depends on 13) The semiconductor device as recited in claim 13, further comprising: a fifth linear-shaped conductive structure defined in the given chip level of the semiconductor device, the fifth linear-shaped conductive structure having a lengthwise centerline oriented in the first direction, the fifth linear-shaped conductive structure having a width measured in the second direction, the fifth linear-shaped conductive structure positioned in the second direction between the fourth and third linear-shaped conductive structures. ### Claim 16 (depends on 15) The semiconductor device as recited in claim 15, wherein at least a portion of the fifth linear-shaped conductive structure is positioned in a side-by-side manner with at least a portion of the fourth linear-shaped conductive structure, the side-by-side positioned portions of the fourth and fifth linear-shaped conductive structures separated from each other by the first distance as measured in the second direction. ### Claim 17 (depends on 16) The semiconductor device as recited in claim 16, wherein at least a portion of the fifth linear-shaped conductive structure is positioned in a side-by-side manner with at least a portion of the third linear-shaped conductive structure, the side-by-side positioned portions of the third and fifth linear-shaped conductive structures separated from each other by the first distance as measured in the second direction. ### Claim 18 (depends on 17) The semiconductor device as recited in claim 17, wherein the width of the fourth linear-shaped conductive structure is substantially equal to the width of the first linear-shaped conductive structure, and wherein the width of the fifth linear-shaped conductive structure is substantially equal to the width of the first linear-shaped conductive structure. ### Claim 19 (depends on 17) The semiconductor device as recited in claim 17, wherein the first linear-shaped conductive structure has a first end and a second end and extends in the first direction from its first end to its second end, wherein the second linear-shaped conductive structure has a first end and a second end and extends in the first direction from its first end to its second end, wherein the third linear-shaped conductive structure has a first end and a second end and extends in the first direction from its first end to its second end, wherein the fourth linear-shaped conductive structure has a first end and a second end and extends in the first direction from its first end to its second end, wherein the fifth linear-shaped conductive structure has a first end and a second end and extends in the first direction from its first end to its second end, wherein the first ends of the first, second, and third linear-shaped conductive structures are substantially positioned on a first line oriented in the second direction, wherein the second ends of the first and second linear-shaped conductive structures are substantially positioned on a second line oriented in the second direction, wherein the first ends of the fourth and fifth linear-shaped conductive structures are substantially positioned on a third line oriented in the second direction, and wherein a region of the given chip level located between the first and third linear-shaped conductive structures and located between the second and third lines oriented in the second direction does not include any conductive structure. ### Claim 20 A method for creating a layout of a semiconductor device, comprising: operating a computer to define a layout of a first linear-shaped conductive structure defined in a given chip level of the semiconductor device, the first linear-shaped conductive structure having a lengthwise centerline oriented in a first direction, the first linear-shaped conductive structure having a width measured in a second direction perpendicular to the first direction; operating a computer to define a layout of a second linear-shaped conductive structure defined in the given chip level of the semiconductor device, the second linear-shaped conductive structure having a lengthwise centerline oriented in the first direction, the second linear-shaped conductive structure having a width measured in the second direction; and operating a computer to define a layout of a third linear-shaped conductive structure defined in the given chip level of the semiconductor device, the third linear-shaped conductive structure having a lengthwise centerline oriented in the first direction, the third linear-shaped conductive structure having a width measured in the second direction, the width of the first linear-shaped conductive structure substantially equal to the width of the third linear-shaped conductive structure, the width of the second linear-shaped conductive structure greater than the width of the first linear-shaped conductive structure, at least a portion of the second linear-shaped conductive structure positioned in a side-by-side manner with at least a portion of the first linear-shaped conductive structure, the side-by-side positioned portions of the first and second linear-shaped conductive structure separated from each other by a first distance as measured in the second direction, and at least a portion of the second linear-shaped conductive structure positioned in a side-by-side manner with at least a portion of the third linear-shaped conductive structure, the side-by-side positioned portions of the second and third linear-shaped conductive structures separated from each other by the first distance as measured in the second direction. ### Claim 21 A data storage device having program instructions stored thereon for generating a layout of a semiconductor device, comprising: program instructions for defining a layout of a first linear-shaped conductive structure defined in a given chip level of the semiconductor device, the first linear-shaped conductive structure having a lengthwise centerline oriented in a first direction, the first linear-shaped conductive structure having a width measured in a second direction perpendicular to the first direction; program instructions for defining a layout of a second linear-shaped conductive structure defined in the given chip level of the semiconductor device, the second linear-shaped conductive structure having a lengthwise centerline oriented in the first direction, the second linear-shaped conductive structure having a width measured in the second direction; and program instructions for defining a layout of a third linear-shaped conductive structure defined in the given chip level of the semiconductor device, the third linear-shaped conductive structure having a lengthwise centerline oriented in the first direction, the third linear-shaped conductive structure having a width measured in the second direction, the width of the first linear-shaped conductive structure substantially equal to the width of the third linear-shaped conductive structure, the width of the second linear-shaped conductive structure greater than the width of the first linear-shaped conductive structure, at least a portion of the second linear-shaped conductive structure positioned in a side-by-side manner with at least a portion of the first linear-shaped conductive structure, the side-by-side positioned portions of the first and second linear-shaped conductive structure separated from each other by a first distance as measured in the second direction, and at least a portion of the second linear-shaped conductive structure positioned in a side-by-side manner with at least a portion of the third linear-shaped conductive structure, the side-by-side positioned portions of the second and third linear-shaped conductive structures separated from each other by the first distance as measured in the second direction.