# US 2014/0197542 A1 · Semiconductor devices and methods of fabricating semiconductor devices

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 2014/0197542 A1
- Document ID: US20140197542A1
- Status: Published application
- Kind: A1
- Application number: 14/155,649
- Filed: 2014-01-15
- Published: 2014-07-17
- Earliest claimed: 2013-01-17
- Assignees: Samsung Electronics Co., Ltd.
- Inventors: Jang-Gn Yun; Hongsoo Kim; Aaron Park; Hoosung Cho
- Web page: https://patentgrep.com/patent/US20140197542A1

## CPC

- H10B 43/35: with cell select transistors, e.g. NAND
- H10B 43/27: the channels comprising vertical portions, e.g. U-shaped channels
- H10B 43/50: characterised by the boundary region between the core and peripheral circuit regions
- H10B: ELECTRONIC MEMORY DEVICES

## Abstract

Semiconductor devices are provided. A semiconductor device may include a substrate and a plurality of lines on the substrate. The semiconductor device may include a dielectric layer on the substrate and adjacent the plurality of lines. The semiconductor device may include a connection element in the dielectric layer. In some embodiments, the semiconductor device may include a plurality of contacts on the connection element, and a conductive interconnection on one of the plurality of contacts that are on the connection element and on a contact that is spaced apart from the connection element.

## Claims

### Claim 1

A semiconductor device comprising:
a substrate;
spaced-apart first and second conductive lines extending in a first direction on the substrate;
an interlayer dielectric on the first and second conductive lines; and
a connection structure configured to electrically connect the first and second conductive lines, the connection structure comprising a connection element extending in a second direction that intersects the first direction,
wherein an uppermost surface of the connection element is substantially coplanar with an uppermost surface of the interlayer dielectric, relative to an uppermost surface of the substrate, and
wherein a height of a lowermost surface of the connection element is equivalent to or lower than a height of uppermost surfaces of the first and second conductive lines, relative to the uppermost surface of the substrate.

### Claim 2 (depends on 1)

The semiconductor device of claim 1, wherein the connection element contacts the uppermost surfaces of the first and second conductive lines.

### Claim 3 (depends on 1)

The semiconductor device of claim 1, wherein the connection element is vertically non-overlapping with the first and second conductive lines.

### Claim 4 (depends on 3)

The semiconductor device of claim 3, wherein the connection structure further comprises:
first and second contact plugs in the interlayer dielectric and contacting the first and second conductive lines, respectively; and
an interconnection configured to electrically connect the first and second contact plugs and the connection element,
wherein a width of the connection element is wider than a width of either of the first and second contact plugs.

### Claim 5 (depends on 1)

The semiconductor device of claim 1, further comprising a third conductive line between the first and second conductive lines and spaced apart therefrom,
wherein a height of a lowermost surface of the third conductive line is equivalent to or lower than the height of the uppermost surfaces of the first and second conductive lines, relative to the uppermost surface of the substrate.

### Claim 6 (depends on 5)

The semiconductor device of claim 5, wherein the third conductive line and the connection plate comprise an equivalent material.

### Claim 7 (depends on 1)

The semiconductor device of claim 1, wherein:
the semiconductor device further comprises third and fourth conductive lines spaced apart from the first and second conductive lines and adjacent the interlayer dielectric;
the connection structure comprises a first connection structure; and
the semiconductor device further comprises a second connection structure configured to electrically connect the third and fourth conductive lines and spaced apart from the first connection structure,
wherein the first through fourth conductive lines define a step-shaped pattern.

### Claim 8 (depends on 7)

The semiconductor device of claim 7, wherein:
the connection element comprises a first connection element;
the second connection structure comprises a second connection element spaced apart from the first connection element and extending in the second direction, the second connection element comprising an uppermost surface substantially coplanar with the uppermost surface of the interlayer dielectric.

### Claim 9

A semiconductor device comprising:
a substrate;
parallel first conductive lines on the substrate;
parallel second conductive lines spaced apart from the first conductive lines and above the first conductive lines, relative to an uppermost surface of the substrate;
an interlayer dielectric on the first and second conductive lines;
a first connection structure electrically connecting the first conductive lines; and
a second connection structure electrically connecting the second conductive lines,
wherein at least one of the first connection structure and the second connection structure comprises a connection element extending in a first direction that intersects with a second direction in which the first and second conductive lines extend, and
wherein an uppermost surface of the connection element is substantially coplanar with an uppermost surface of the interlayer dielectric and a height of a lowermost surface of the connection element is equivalent to or lower than a height of uppermost surfaces of the first and second conductive lines, relative to the uppermost surface of the substrate.

### Claim 10 (depends on 9)

The semiconductor device of claim 9, wherein the first conductive lines and the second conductive lines define a stepped shape.

### Claim 11 (depends on 9)

The semiconductor device of claim 9, wherein:
the interlayer dielectric comprises a first interlayer dielectric;
the semiconductor device further comprises a second interlayer dielectric on the first interlayer dielectric;
the first connection structure comprises:
a first connection element contacting the first conductive lines;
a first connection contact in the second interlayer dielectric and contacting the first connection element; and
a first connection interconnection contacting the first connection contact;
the second connection structure comprises:
a second connection element contacting the second conductive lines;
a second connection contact in the second interlayer dielectric and contacting the second connection element; and
a second connection interconnection contacting the second connection contact; and
the first connection interconnection and the second connection interconnection are spaced apart from each other.

### Claim 12 (depends on 9)

The semiconductor device of claim 9, wherein:
the interlayer dielectric comprises a first interlayer dielectric;
the semiconductor device further comprises a second interlayer dielectric on the first interlayer dielectric;
the first connection structure comprises:
a first connection element contacting the first conductive lines;
a first connection contact in the second interlayer dielectric and contacting the first connection element; and
a first connection interconnection contacting the first connection contact;
the second connection structure comprises:
a second connection contact that contacts the second conductive lines;
a third connection contact in the second interlayer dielectric and contacting the second connection contact;
a second connection interconnection contacting the third connection contact;
a fourth connection contact in the second interlayer dielectric and spaced apart from the third connection contact; and
a second connection element that contacts the fourth connection contact, is in the first interlayer dielectric, and is spaced apart from the second conductive lines; and
the first connection interconnection and the second connection interconnection are spaced apart from each other.

### Claim 13 (depends on 9)

The semiconductor device of claim 9, wherein:
the interlayer dielectric comprises a first interlayer dielectric;
the semiconductor device further comprises a second interlayer dielectric on the first interlayer dielectric;
the first connection structure comprises:
a first connection contact that contacts the first conductive lines;
a second connection contact in the second interlayer dielectric and contacting the first connection contact; and
a first connection interconnection contacting the second connection contact;
the second connection structure comprises:
a third connection contact that contacts the second conductive lines;
a fourth connection contact in the second interlayer dielectric and contacting the third connection contact;
a second connection interconnection contacting the fourth connection contact;
a fifth connection contact in the second interlayer dielectric and spaced apart from the fourth connection contact; and
the connection element that contacts the fifth connection contact, is in the first interlayer dielectric, and is spaced apart from the second conductive lines; and
the first connection interconnection and the second connection interconnection are spaced apart from each other.

### Claim 14

A semiconductor device comprising:
a substrate;
a plurality of word lines on the substrate;
a dielectric layer on the substrate and adjacent the plurality of word lines;
a connection element comprising a conductive material in the dielectric layer;
a plurality of contacts on the connection element; and
a conductive interconnection on one of the plurality of contacts that are on the connection element and on a contact that is spaced apart from the connection element.

### Claim 15 (depends on 14)

The semiconductor device of claim 14, further comprising a selection line underlying the plurality of word lines, wherein the contact that is spaced apart from the connection element overlaps the selection line.

### Claim 16 (depends on 15)

The semiconductor device of claim 15, wherein the connection element is spaced apart from, and non-overlapping with, the plurality of word lines and the selection line.

### Claim 17 (depends on 16)

The semiconductor device of claim 16, further comprising a common source line underlying the dielectric layer, wherein the connection element overlaps the common source line.

### Claim 18 (depends on 14)

The semiconductor device of claim 14, wherein:
the one of the plurality of contacts on the connection element comprises a first contact on the connection element;
the semiconductor device further comprises a second contact, among the plurality of contacts, on the connection element;
the conductive interconnection comprises a first conductive interconnection;
the semiconductor device further comprises a second conductive interconnection on the second contact that is on the connection element and on another contact that is spaced apart from the connection element; and
the semiconductor device further comprises a third conductive interconnection that is between the first and second conductive interconnections and that overlaps the plurality of word lines.

### Claim 19 (depends on 18)

The semiconductor device of claim 18, further comprising:
a selection line underlying the plurality of word lines; and
a connection contact configured to electrically connect the selection line to one of:
the contact that is spaced apart from the connection element; and
the another contact that is spaced apart from the connection element.

### Claim 20 (depends on 19)

The semiconductor device of claim 19, wherein:
the connection contact comprises a first connection contact; and
the semiconductor device further comprises a second connection contact that is configured to electrically connect the third conductive interconnection to one of the plurality of word lines.