# US 2014/0197540 A1 · Extended Redistribution Layers Bumped Wafer

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- Number: US 2014/0197540 A1
- Document ID: US20140197540A1
- Status: Published application
- Kind: A1
- Application number: 14/214,120
- Filed: 2014-03-14
- Published: 2014-07-17
- Earliest claimed: 2007-05-04
- Assignees: STATS ChipPAC, Ltd.
- Applicants: STATS ChipPAC, Ltd.
- Inventors: Byung Tai Do; Heap Hoe Kuan
- Web page: https://patentgrep.com/patent/US20140197540A1

## CPC

- H10W 72/0198: {batch processes}
- H10P 72/74: {using temporarily an auxiliary support}
- H10P 72/7402: {Wafer tapes, e.g. grinding or dicing support tapes}
- H10W 72/019: {of bond pads}
- H10W 74/019: {using temporary auxiliary substrates (H10W74/017 takes precedence)}
- H10P 72/7416: {used during dicing or grinding}
- H10P 72/743: {used as a support during manufacture of interconnect decals or build up layers}
- H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40)
- H10W 70/655: Fan-out layouts
- H10W 72/01225: {in solid form, e.g. by using a powder or by stud bumping}
- H10W 72/241: {Dispositions, e.g. layouts}
- H10W 72/248: {Top-view layouts, e.g. mirror arrays}
- H10W 72/251: {Materials}
- H10W 72/252: {comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu}
- H10W 72/29: Bond pads specially adapted therefor
- H10W 72/922: {Bond pads being integral with underlying chip-level interconnections}
- H10W 72/9413: {on encapsulations}
- H10W 74/129: {forming a chip-scale package [CSP]}
- H10W 74/141: {the encapsulations being on at least the sidewalls of the semiconductor body}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor device is manufactured by, first, providing a wafer, designated with a saw street guide, and having a bond pad formed on an active surface of the wafer. The wafer is taped with a dicing tape. The wafer is singulated along the saw street guide into a plurality of dies having a plurality of gaps between each of the plurality of dies. The dicing tape is stretched to expand the plurality of gaps to a predetermined distance. An organic material is deposited into each of the plurality of gaps. A top surface of the organic material is substantially coplanar with a top surface of a first die of the plurality of dies. A redistribution layer is patterned over a portion of the organic material. An under bump metallization (UBM) is deposited over the organic material in electrical communication, through the redistribution layer, with the bond pad.

## Claims

### Claim 1

A method of making a semiconductor device, comprising:
providing a plurality of semiconductor die;
forming an insulating layer around the semiconductor die;
forming a conductive layer over the insulating layer and semiconductor die;
forming an under bump metallization (UBM) over the insulating layer; and
forming an interconnect structure over the UBM.

### Claim 2 (depends on 1)

The method of claim 1, further including:
disposing the semiconductor die over a dicing tape; and
stretching the dicing tape.

### Claim 3 (depends on 1)

The method of claim 1, further including disposing the semiconductor die over a substrate with a physical separation between adjacent semiconductor die.

### Claim 4 (depends on 1)

The method of claim 1, wherein the interconnect structure includes a bump.

### Claim 5 (depends on 1)

The method of claim 1, wherein the UBM includes a non-refractory metal and a binary metal alloy.

### Claim 6 (depends on 1)

The method of claim 1, further including forming a surface of the insulating layer substantially coplanar with a surface of the semiconductor die.

### Claim 7

A method of making a semiconductor device, comprising:
providing a semiconductor die;
forming an insulating layer around the semiconductor die;
forming a conductive layer over the insulating layer and semiconductor die; and
forming a first under bump metallization (UBM) over the insulating layer.

### Claim 8 (depends on 7)

The method of claim 7, further including forming an interconnect structure over the first UBM.

### Claim 9 (depends on 7)

The method of claim 7, further including:
forming a second UBM over the semiconductor die; and
forming an interconnect structure over the second UBM.

### Claim 10 (depends on 7)

The method of claim 7, wherein the first UBM includes a refractory metal.

### Claim 11 (depends on 7)

The method of claim 7, further including disposing the semiconductor die over a dicing tape.

### Claim 12 (depends on 7)

The method of claim 7, further including disposing the semiconductor die over a substrate.

### Claim 13 (depends on 12)

The method of claim 12, wherein the substrate includes glass, ceramic, laminate, or silicon.

### Claim 14

A semiconductor device, comprising:
a semiconductor die;
an insulating layer formed around the semiconductor die;
a conductive layer formed over the insulating layer; and
a first under bump metallization (UBM) formed over the insulating layer.

### Claim 15 (depends on 14)

The semiconductor device of claim 14, wherein a surface of the insulating layer is substantially coplanar with a surface of the semiconductor die.

### Claim 16 (depends on 14)

The semiconductor device of claim 14, further including a second UBM formed over the semiconductor die.

### Claim 17 (depends on 14)

The semiconductor device of claim 14, further including a dicing tape disposed over the semiconductor die.

### Claim 18 (depends on 14)

The semiconductor device of claim 14, further including a substrate disposed over the semiconductor die.

### Claim 19 (depends on 14)

The semiconductor device of claim 14, further including an interconnect structure formed over the first UBM.

### Claim 20 (depends on 14)

The semiconductor device of claim 14, wherein the first UBM includes a refractory metal.

### Claim 21

A semiconductor device, comprising:
a semiconductor die;
an insulating layer formed coplanar with opposing surfaces of the semiconductor die; and
a conductive layer formed over the insulating layer.

### Claim 22 (depends on 21)

The semiconductor device of claim 21, further including an under bump metallization formed over the insulating layer.

### Claim 23 (depends on 21)

The semiconductor device of claim 21, further including an interconnect structure formed over the insulating layer.

### Claim 24 (depends on 21)

The semiconductor device of claim 21, further including a substrate disposed over the semiconductor die.

### Claim 25 (depends on 24)

The semiconductor device of claim 24, wherein the substrate includes a dicing tape, glass, ceramic, laminate, or silicon.