# US 2014/0197538 A1 · Copper etching integration scheme

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- Number: US 2014/0197538 A1
- Document ID: US20140197538A1
- Status: Published application
- Kind: A1
- Application number: 14/218,060
- Filed: 2014-03-18
- Published: 2014-07-17
- Earliest claimed: 2012-11-14
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Co., Ltd.
- Inventors: Chih-Wei Lu; Chung-Ju Lee; Hsiang-Huan Lee; Tien-I Bao
- Web page: https://patentgrep.com/patent/US20140197538A1

## CPC

- H10W 20/435: {Cross-sectional shapes or dispositions of interconnections}
- H10D 62/115: {Dielectric isolations, e.g. air gaps}
- H10P 50/71: {using masks for conductive or resistive materials}
- H10P 95/062: {involving a dielectric removal step}
- H10W 20/039: {also covering sidewalls of the conductive structures}
- H10W 20/063: {by forming conductive members before forming protective insulating material}
- H10W 20/0633: {using subtractive patterning of the conductive members}
- H10W 20/067: {by modifying the pattern of conductive parts}
- H10W 20/069: {by forming self-aligned vias or self-aligned contact plugs}
- H10W 20/0693: {by forming self-aligned vias}
- H10W 20/072: {of dielectric parts comprising air gaps}
- H10W 20/42: Vias, e.g. via plugs
- H10W 20/425: {Barrier, adhesion or liner layers}
- H10W 20/4405: {the principal metal being aluminium}
- H10W 20/4421: {the principal metal being copper}
- H10W 20/4424: {Copper alloys}
- H10W 20/4441: {the principal metal being a refractory metal}
- H10W 20/46: comprising air gaps
- H10W 20/47: comprising two or more dielectric layers having different properties, e.g. different dielectric constants
- H10W 20/48: Insulating materials thereof
- H10W 70/611: {for connecting multiple chips together}
- H10W 70/635: {Through-vias}
- H10W 70/65: Shapes or dispositions of interconnections
- H10W 20/495: {Capacitive arrangements or effects of, or between wiring layers}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

The present disclosure is directed to an interconnect structure. The metal interconnect structure has a metal body disposed over a semiconductor substrate and a projection extending from the metal body. A barrier layer continuously extends over the projection from a first sidewall of metal body to an opposing second sidewall of the metal body. A layer of dielectric material is disposed over the semiconductor substrate at a position abutting the metal body and the projection.

## Claims

### Claim 1

An interconnect structure, comprising:
a metal body disposed over a semiconductor substrate;
a projection extending outward from a top surface of the metal body;
a barrier layer continuously extending over the projection from a first sidewall of the metal body to an opposing, second sidewall of the metal body; and
a layer of dielectric material disposed over the semiconductor substrate at a position abutting the metal body and the projection.

### Claim 2 (depends on 1)

The interconnect structure of claim 1, wherein the barrier layer is not on bottom surface of the metal body, so that the metal body abuts a metal layer underlying the metal body.

### Claim 3 (depends on 1)

The interconnect structure of claim 1, wherein the metal body comprises a metal wire configured to provide a lateral interconnection and the projection comprises a metal via configured to provide a vertical interconnection.

### Claim 4 (depends on 1)

The interconnect structure of claim 1, wherein the metal body includes angled opposing sidewalls which taper to give the metal body a top surface that is wider than a bottom surface.

### Claim 5 (depends on 1)

The interconnect structure of claim 1, wherein the projection includes angled opposing sidewalls which taper to give the projection a bottom surface that is wider than a top surface.

### Claim 6 (depends on 1)

The interconnect structure of claim 1, wherein the metal body and the projection comprise aluminum (Al), tungsten (W), copper (Cu), copper manganese (CuMn), copper-titanium (CuTi), copper vanadium (CuV), copper chromium (CuCr), or copper-niobium (CuNb).

### Claim 7 (depends on 1)

The interconnect structure of claim 1, further comprising an additional metal layer, comprising:
an additional metal body overlying the projection and electrically coupled to the projection; and
an additional projection overlying the additional metal body.

### Claim 8 (depends on 7)

The interconnect structure of claim 7, further comprising:
an additional layer of dielectric material disposed over the semiconductor substrate at a position laterally abutting the additional metal body and the additional projection,
wherein the additional layer of dielectric material abuts the layer of dielectric material.

### Claim 9 (depends on 1)

The interconnect structure of claim 1, further comprising:
at least one air gap within the layer of dielectric material and between angled sidewalls of adjacent metal bodies.

### Claim 10

A metal interconnect structure, comprising:
a metal wire overlying a semiconductor substrate;
a metal via disposed onto and in direct contact with a top surface of the metal wire, wherein the metal via includes angled opposing sidewalls which taper to give the metal via a bottom surface that is wider than a top surface; and
a layer of dielectric material surrounding the metal wire and the metal via.

### Claim 11 (depends on 10)

The metal interconnect structure of claim 10, further comprising at least one air gap disposed within the layer of dielectric material.

### Claim 12 (depends on 10)

The metal interconnect structure of claim 10, further comprising:
a barrier layer continuously extending over the metal via from a first sidewall of metal wire to an opposing second sidewall of the metal wire.

### Claim 13 (depends on 12)

The metal interconnect structure of claim 12, wherein the barrier layer is not on bottom surface of the metal wire, so that the metal wire abuts a metal layer underlying the metal wire.

### Claim 14 (depends on 10)

The interconnect structure of claim 10, further comprising:
an additional metal wire overlying the metal via;
an additional metal via disposed onto and in direct contact with a top surface of the additional metal wire; and
an additional layer of dielectric material disposed over the semiconductor substrate at a position laterally abutting the additional metal wire and the additional metal via, and abutting the layer of dielectric material.

### Claim 15

An integrated circuit, comprising:
a metal body disposed over a semiconductor substrate;
a projection disposed onto and in direct contact with a top surface of the metal body;
a dielectric material surrounding the metal body and the projection; and
a barrier layer disposed between the dielectric material and the metal body and the projection, wherein the barrier layer does not abut a bottom surface of the metal body.

### Claim 16 (depends on 15)

The integrated circuit of claim 15, wherein the barrier layer comprises a continuous layer that encompass opposing sidewalls of the metal body and the projection disposed onto and in direct contact with the top surface of the metal body.

### Claim 17 (depends on 15)

The integrated circuit of claim 15, wherein the projection includes angled opposing sidewalls which taper to give the projection a bottom surface that is wider than a top surface.

### Claim 18 (depends on 15)

The integrated circuit of claim 15, wherein the dielectric material continuously extends from the bottom surface of the metal body to a top surface of the projection.

### Claim 19 (depends on 15)

The integrated circuit of claim 15, wherein the metal body and the projection comprise aluminum (Al), tungsten (W), copper (Cu), copper manganese (CuMn), copper-titanium (CuTi), copper vanadium (CuV), copper chromium (CuCr), or copper-niobium (CuNb).

### Claim 20 (depends on 15)

The integrated circuit of claim 15, further comprising at least one air gap within the dielectric material.