# US 2014/0197536 A1 · Package structure and method for manufacturing thereof > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2014/0197536 A1 - Document ID: US20140197536A1 - Status: Published application - Kind: A1 - Application number: 14/152,970 - Filed: 2014-01-10 - Published: 2014-07-17 - Earliest claimed: 2013-01-11 - Assignees: Xintec Inc. - Applicants: Xintec Inc. - Inventors: Ming-Chung CHUNG - Web page: https://patentgrep.com/patent/US20140197536A1 ## CPC - H10W 20/063: {by forming conductive members before forming protective insulating material} - H10D 62/117: {Shapes of semiconductor bodies} - H10W 70/65: Shapes or dispositions of interconnections - H10W 72/0198: {batch processes} - H10W 72/244: {relative to underlying supporting features, e.g. bond pads, RDLs or vias} - H10W 72/252: {comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu} - H10W 72/877: {Bump connectors and die-attach connectors} - H10W 74/014: {using batch processing} - H10W 74/129: {forming a chip-scale package [CSP]} - H10W 74/137: {the encapsulations being directly on the semiconductor body (H10W74/134 takes precedence)} - H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL} - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES ## Abstract The invention provides an electronic device package and method for manufacturing thereof. The electronic device package includes a substrate, an electronic chip, a bonding pad, a first passivation layer, a conductive layer, a second passivation layer, and a solder ball. The conductive layer has a first side end and a second side end, and the solder ball is positioned on the first side end of the conductive layer. The second passivation layer contacts with both the upper surface and the sidewall of the second side end of the conductive layer, and the first passivation layer contacts with the lower surface of the second side end of the conductive layer, so as to completely encapsulate the second end of the conductive layer. The electronic device package accordingly prevents the moisture penetration and to enhance the reliability of the electronic device. ## Claims ### Claim 1 An electronic device package structure, comprising: a substrate; an electronic chip positioned on the substrate; a boding pad sandwiched between the substrate and the electronic chip, and electrically connected to the electronic chip; a first passivation layer sandwiched between the substrate and the bonding pad; a conductive layer positioned on a sidewall of the electronic chip and electrically connected to the bonding pad, the conductive layer comprising a first side end and a second side end opposite to the first side end, wherein the bottom surface of the second side end contacts the first passivation layer; a second passivation layer positioned on the conductive layer, exposing the first side end of the conductive layer and covering the second side end of the conductive layer, wherein the second passivation layer simultaneously contacts the top surface and a sidewall of the conductive layer, and completely covers the second side end of the conductive layer with the first passivation layer; and a solder ball positioned on the exposed first side end of the conductive layer. ### Claim 2 (depends on 1) The electronic device package structure of claim 1, wherein the electronic chip comprises an integrated circuit device, a photoelectric device, a microelectromechanical (MEM) device, a surface acoustic wave (SAW) device or a combination thereof. ### Claim 3 (depends on 1) The electronic device package structure of claim 1, wherein the first passivation layer comprises epoxy resin, polyimide (PI) resin, silicon oxide, metal oxide or silicon nitride. ### Claim 4 (depends on 1) The electronic device package structure of claim 1, wherein the conductive layer comprises copper (Cu), aluminum (Al), nickel (Ni), gold (Au) or a combination thereof. ### Claim 5 (depends on 1) The electronic device package structure of claim 1, wherein the second passivation layer comprises epoxy resin, polyimide (PI) resin, silicon oxide, metal oxide or silicon nitride. ### Claim 6 (depends on 1) The electronic device package structure of claim 1, further comprising a barrier layer sandwiched between the substrate and the electronic chip. ### Claim 7 (depends on 6) The electronic device package structure of claim 6, wherein the bonding pad and the barrier layer are on the same surface. ### Claim 8 (depends on 6) The electronic device package structure of claim 6, wherein the barrier layer comprises epoxy resin, polyimide (PI) resin, silicon oxide, metal oxide or silicon nitride. ### Claim 9 (depends on 1) The electronic device package structure of claim 1, further comprising an adhesive layer sandwiched between the conductive layer and the electronic chip. ### Claim 10 (depends on 9) The electronic device package structure of claim 9, wherein the adhesive layer comprises epoxy resin, polyimide (PI) resin, silicon oxide, metal oxide or silicon nitride. ### Claim 11 A method for manufacturing an electronic device package structure, comprising: providing a semiconductor wafer including a plurality of electronic chips; forming a bonding pad under each of the electronic chips and electrically connected to each of the electronic chips; forming a first passivation layer under the bonding pad; forming a conductive layer on a sidewall of each of the electronic chips and electrically connected to the bonding pad, wherein the conductive layer comprises a first side end and a second side end, wherein the bottom surface of the second side end of the conductive layer contacts the first passivation layer, and the respective conductive layers on the sidewalls of the adjacent electronic chips are not connected to each other; forming a second passivation layer on the conductive layer, exposing the first side end of the conductive layer and covering the second side end of the conductive layer, wherein the second passivation layer simultaneously contacts the top surface and a sidewall of the conductive layer, and completely covers the second side end of the conductive layer with the first passivation layer; forming a solder ball on the first side end of the conductive layer; and dicing a disconnection area of the conductive layers between the adjacent electronic chips to separate the electronic chips. ### Claim 12 (depends on 11) The method of claim 11, further comprising: providing a substrate; and forming a barrier layer sandwiched between the substrate and each of the electronic chips. ### Claim 13 (depends on 11) The method of claim 11, further comprising forming an adhesive layer sandwiched between each of the electronic chips and the conductive layer. ### Claim 14 (depends on 11) The method of claim 11, wherein forming the conductive layer comprises: forming a conductive layer on the sidewall of each of the electronic chips and electrically connected to the bonding pad; forming a photo-resist layer on the conductive layer; etching part of the conductive layer, so that the conductive layer is disconnected from a conductive layer of an adjacent electronic device package structure; removing the photo-resist layer; and depositing a metal on the conductive layer to thicken the conductive layer. ### Claim 15 (depends on 14) The method of claim 14, wherein forming the photo-resist layer comprises: coating a photo-resist agent on the conductive layer to form a photo-resist layer; applying a mask to form one of a plurality of sub-patterns on the photo-resist layer; and removing part of the photo-resist layer to expose part of the conductive layer, wherein the sub-patterns are individually corresponded to the electronic chips, and each of the sub-patterns and the adjacent one of the sub-patterns have a separating channel therebetween; after part of the photo-resist layer is removed, the photo-resist layer corresponded to the separated channel forms a recess, so as to disconnect the conductive layer from the conductive layer of the adjacent electronic device package structure. ### Claim 16 (depends on 15) The method of claim 15, wherein the photo-resist agent is a positive photo-resist agent, and the mask is a dark mask. ### Claim 17 (depends on 15) The method of claim 15, wherein the photo-resist agent is a negative photo-resist agent, and the mask is a clear mask. ### Claim 18 (depends on 11) The method of claim 11, wherein forming the conductive layer comprises: forming a conductive layer on the sidewall of each of the electronic chips and electrically connected to the bonding pad; forming a photo-resist layer on the conductive layer; depositing metal on the conductive layer to thicken the conductive layer; removing the photo-resist layer; and etching part of the conductive layer, so that the conductive layer is disconnected from a conductive layer of an adjacent electronic device package structure. ### Claim 19 (depends on 18) The method of claim 18, wherein forming the photo-resist layer comprises: coating a photo-resist agent on the conductive layer to form a photo-resist layer; applying a mask to form one of a plurality of sub-patterns on the photo-resist layer; and removing part of the photo-resist layer to expose part of the conductive layer, wherein the sub-patterns are individually corresponded to the electronic chips, and each of the sub-patterns and the adjacent one of the sub-patterns have a separating channel therebetween; after part of the photo-resist layer is removed, the photo-resist layer corresponded to the separated channel forms a embossment, so as to disconnect the conductive layer from the conductive layer of the adjacent electronic device package structure. ### Claim 20 (depends on 19) The method of claim 19, wherein the photo-resist agent is a positive or negative photo-resist agent, and the mask is a clear or dark mask.