# US 2014/0197535 A1 · Wafer-level packaging mechanisms

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- Number: US 2014/0197535 A1
- Document ID: US20140197535A1
- Status: Published application
- Kind: A1
- Application number: 14/211,341
- Filed: 2014-03-14
- Published: 2014-07-17
- Earliest claimed: 2012-05-18
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Company, Ltd.
- Inventors: Jing-Cheng LIN; Jui-Pin HUNG
- Web page: https://patentgrep.com/patent/US20140197535A1

## CPC

- H10W 72/20: Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
- H10W 70/09: extending onto an encapsulation that laterally surrounds the chip or wafer, e.g. fan-out wafer level package [FOWLP] RDLs
- H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40)
- H10W 70/614: {the multiple chips being integrally enclosed}
- H10W 70/685: comprising multiple insulating layers
- H10W 74/019: {using temporary auxiliary substrates (H10W74/017 takes precedence)}
- H10W 70/099: {Connecting interconnections to insulating or insulated package substrates, interposers or redistribution layers}
- H10W 72/241: {Dispositions, e.g. layouts}
- H10W 72/252: {comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu}
- H10W 72/29: Bond pads specially adapted therefor
- H10W 72/9413: {on encapsulations}
- H10W 74/00: Encapsulations, e.g. protective coatings
- H10W 74/142: {the encapsulations exposing the passive side of the semiconductor body}
- H10W 90/10: Configurations of laterally-adjacent chips
- H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor package includes a first semiconductor die surrounded by a molding compound. The semiconductor package further includes a first conductive pad on the first semiconductor die, wherein the first conductive pad is at a top metal level of the first semiconductor die. The semiconductor package further includes redistribution lines (RDLs) formed over the first conductive pad, wherein at least one RDL of the RDLs extends beyond the boundaries of the semiconductor die, and a portion of the at least one RDL contacts the first conductive pad, wherein a surface of the first conductive pad contacting the portion of the at least one RDL is at a different level than a surface of the molding compound under the at least one RDL extended beyond the boundaries of the first semiconductor die.

## Claims

### Claim 1

A semiconductor package comprising:
a first semiconductor die surrounded by a molding compound;
a first conductive pad on the first semiconductor die, wherein the first conductive pad is at a top metal level of the first semiconductor die; and
redistribution lines (RDLs) formed over the first conductive pad, wherein at least one RDL of the RDLs extends beyond the boundaries of the semiconductor die, and a portion of the at least one RDL contacts the first conductive pad, wherein a surface of the first conductive pad contacting the portion of the at least one RDL is at a different level than a surface of the molding compound under the at least one RDL extended beyond the boundaries of the first semiconductor die.

### Claim 2 (depends on 1)

The semiconductor package of claim 1, wherein the at least one RDL contacts the first conductive pad through at least one conductive plug.

### Claim 3 (depends on 1)

The semiconductor package of claim 1, wherein a difference in height between the surface of the first conductive pad and the surface of the molding compound is in a range from about 5 μm to about 100 μm.

### Claim 4 (depends on 1)

The semiconductor package of claim 1, further comprising:
a second semiconductor die, wherein the second semiconductor die includes a stud bump over a second conductive pad over the second semiconductor die.

### Claim 5 (depends on 4)

The semiconductor package of claim 4, wherein a surface of the stud bump is at substantially a same level as the surface of the molding compound.

### Claim 6 (depends on 4)

The semiconductor package of claim 4, wherein the stud bump is made of a material comprising aluminum, copper, an alloy thereof, or a combination thereof.

### Claim 7 (depends on 4)

The semiconductor package of claim 4, wherein the second semiconductor die has fewer inputs/outputs (I/Os) than the first semiconductor die.

### Claim 8 (depends on 1)

The semiconductor package of claim 1, wherein the surface of the molding compound is substantially flat.

### Claim 9 (depends on 4)

The semiconductor of claim 4, wherein the molding compound surrounds the stud bump.

### Claim 10

A semiconductor package comprising:
a molding compound surrounding a first semiconductor die;
a first conductive pad on the first semiconductor die, wherein the first conductive pad is at a top metal level of the first semiconductor die; and
a redistribution line (RDL) over the first conductive pad, wherein the RDL extends over a top surface of the molding compound, and a portion of the RDL is electrically connected to the first conductive pad, and a surface of the first conductive pad electrically connected to the portion of the RDL is at a different level from the top surface of the molding compound.

### Claim 11 (depends on 10)

The semiconductor package of claim 10, further comprising a second semiconductor die spaced from the first semiconductor die, the second semiconductor die surrounded by the molding compound, wherein the RDL is electrically connected to the second semiconductor die.

### Claim 12 (depends on 10)

The semiconductor package of claim 10, wherein the molding compound comprises a dielectric material.

### Claim 13 (depends on 10)

The semiconductor package of claim 10, further comprising an electrical connector electrically connected to the RDL, wherein the electrical connector is located outside a boundary of the first semiconductor die.

### Claim 14 (depends on 10)

The semiconductor package of claim 10, wherein a bottom surface of the first semiconductor die is substantially level with a bottom surface of the molding compound.

### Claim 15 (depends on 10)

The semiconductor package of claim 10, further comprising a stud bump on the first conductive pad, wherein the RDL is electrically connected to the first conductive pad through the stud bump.

### Claim 16 (depends on 15)

The semiconductor package of claim 15, wherein the molding compound extends over a top surface of the first semiconductor die, and a top surface of the stud bump is substantially level with the top surface of the molding compound.

### Claim 17

A semiconductor package comprising:
a first semiconductor die;
a second semiconductor die spaced from the first semiconductor die;
a first conductive pad on the first semiconductor die;
a second conductive pad on the second semiconductor die;
a dielectric layer surrounding the first semiconductor die and the second semiconductor die;
a redistribution line (RDL) electrically connected to the first conductive pad and to the second conductive pad, wherein the RDL extends over a top surface of the dielectric layer, and a surface of the first conductive pad electrically connected to the portion of the RDL is at a different level from the top surface of the dielectric layer.

### Claim 18 (depends on 17)

The semiconductor package of claim 17, further comprising a stud bump on the second conductive pad, wherein a top surface of the stud bump is substantially level with the top surface of the dielectric layer.

### Claim 19 (depends on 17)

The semiconductor package of claim 17, wherein the dielectric layer comprises at least one of a molding compound, an underfill, or an epoxy.

### Claim 20 (depends on 17)

The semiconductor package of claim 17, further comprising an electrical connector electrically connected to the RDL, wherein the electrical connector is over the top surface of the dielectric layer and located outside a boundary of the first semiconductor die.