# US 2014/0197533 A1 · Semiconductor device and method for manufacturing the semiconductor device

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- Number: US 2014/0197533 A1
- Document ID: US20140197533A1
- Status: Published application
- Kind: A1
- Application number: 14/133,859
- Filed: 2013-12-19
- Published: 2014-07-17
- Earliest claimed: 2013-01-15
- Assignees: Fujitsu Semiconductor Limited
- Applicants: Fujitsu Semiconductor Limited
- Inventors: Takeshi Imamura; Nobutaka Shimizu; YASUNORI FUJIMOTO
- Web page: https://patentgrep.com/patent/US20140197533A1

## CPC

- H10W 40/22: characterised by their shape, e.g. having conical or cylindrical projections
- H10W 40/258: {Metallic materials (H10W40/254, H10W40/257, H10W40/255, H10W40/251, H10W40/253 take precedence)}
- H10W 40/70: Fillings or auxiliary members in containers or in encapsulations for thermal protection or control
- H10W 72/20: Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
- H10W 72/30: Die-attach connectors
- H10W 74/012: {of encapsulations on active surfaces of flip-chip devices, e.g. forming underfills}
- H10W 74/15: on active surfaces of flip-chip devices, e.g. underfills
- H10W 76/12: characterised by their shape
- H10W 90/00: Package configurations
- H10W 72/01325: {in solid form}
- H10W 72/016: {of strap connectors}
- H10W 72/072: {of bump connectors}
- H10W 72/07236: {Soldering or alloying}
- H10W 72/073: {of die-attach connectors}
- H10W 72/07336: {Soldering or alloying}
- H10W 72/07341: {Controlling the bonding environment, e.g. atmosphere composition or temperature}
- H10W 72/252: {comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu}
- H10W 72/29: Bond pads specially adapted therefor
- H10W 72/352: {comprising metals or metalloids, e.g. solders}
- H10W 72/354: {comprising polymers}
- H10W 72/59: Bond pads specially adapted therefor
- H10W 72/877: {Bump connectors and die-attach connectors}
- H10W 72/923: {Bond pads having multiple stacked layers}
- H10W 72/944: {Dispositions of multiple bond pads}
- H10W 72/952: {comprising metals or metalloids, e.g. PbSn, Ag or Cu}
- H10W 72/953: {not comprising solid metals or solid metalloids, e.g. polymers, ceramics or liquids}
- H10W 76/17: characterised by their materials
- H10W 76/67: characterised by their materials
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/736: {between a chip and a stacked lead frame, conducting package substrate or heat sink}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A method for manufacturing a semiconductor device is provided, the method including: mounting a first element on a wiring substrate, placing a first heat sink on the first element with a metal material interposed between the first heat sink and the first element, attaching the first heat sink to the first element via the metal material by heating and melting the metal material, and mounting a second element on the wiring substrate after the steps of attaching the first heat sink to the first element.

## Claims

### Claim 1

A method for manufacturing a semiconductor device, comprising:
mounting a first element on a wiring substrate;
placing a first heat sink on the first element with a metal material interposed between the first heat sink and the first element;
attaching the first heat sink to the first element via the metal material by heating and melting the metal material; and
mounting a second element on the wiring substrate after attaching the first heat sink to the first element.

### Claim 2 (depends on 1)

The method for manufacturing a semiconductor device according to claim 1, further comprising:
attaching a second heat sink onto the second element via a resin material after mounting the second element on the wiring substrate.

### Claim 3 (depends on 2)

The method for manufacturing a semiconductor device according to claim 2, wherein
the resin material used in attaching the second heat sink onto the second element is a thermosetting material, and is cured by being heated at a temperature lower than a melting point of the metal material.

### Claim 4 (depends on 2)

The method for manufacturing a semiconductor device according to claim 2, wherein
the first heat sink includes a frame provided along an edge of the wiring substrate in a plan view, and
the method further comprises:
bonding the frame to the edge.

### Claim 5 (depends on 1)

The method for manufacturing a semiconductor device according to claim 1, further comprising:
forming a metal layer on the first element, before placing the first heat sink on the first element.

### Claim 6 (depends on 1)

The method for manufacturing a semiconductor device according to claim 1, wherein
a surface of the first heat sink beside the first element is provided with a protrusion extending close to the wiring substrate.

### Claim 7 (depends on 1)

The method for manufacturing a semiconductor device according to claim 1, wherein
the second element consumes less power than the first element.

### Claim 8 (depends on 1)

The method for manufacturing a semiconductor device according to claim 1, wherein
the first element is a first active element, and
the second element is a second active element.

### Claim 9 (depends on 8)

The method for manufacturing a semiconductor device according to claim 8, wherein
the first element is a processing unit, and
the second element is a regulator.

### Claim 10 (depends on 1)

The method for manufacturing a semiconductor device according to claim 1, further comprising:
connecting an electronic component to the wiring substrate via solder by heating and melting the solder, before mounting the second element.

### Claim 11 (depends on 1)

The method for manufacturing a semiconductor device according to claim 1, further comprising:
connecting an external connection terminal to the wiring substrate by heating and melting the external connection terminal, before mounting the second element.

### Claim 12

A semiconductor device comprising:
a wiring substrate;
a processing unit mounted on the wiring substrate;
a regulator mounted on the wiring substrate;
a first heat sink attached onto the processing unit via a metal material; and
a second heat sink attached to the regulator via a resin material.

### Claim 13 (depends on 12)

The semiconductor device according to claim 12, wherein
the first heat sink includes a frame provided along an edge of the wiring substrate in a plan view, and
the frame is bonded to the edge.

### Claim 14 (depends on 13)

The semiconductor device according to claim 13, wherein
the second heat sink is bonded to the frame.