# US 2014/0197530 A1 · Semiconductor device with chip having low-k-layers

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- Number: US 2014/0197530 A1
- Document ID: US20140197530A1
- Status: Published application
- Kind: A1
- Application number: 13/739,045
- Filed: 2013-01-11
- Published: 2014-07-17
- Earliest claimed: 2013-01-11
- Assignees: Intel Mobile Communications GmbH
- Inventors: Thorsten Meyer; Sven Albers; Christian Geissler; Andreas Wolter; Markus Brunnbauer; David O'Sullivan; Frank Zudock; Jan Proschwitz
- Web page: https://patentgrep.com/patent/US20140197530A1

## CPC

- H10W 74/124: {the encapsulations having cavities other than that occupied by chips}
- H10W 42/121: {protecting against mechanical damage (H10W76/00, H10W74/00 take precedence)}
- H10W 70/09: extending onto an encapsulation that laterally surrounds the chip or wafer, e.g. fan-out wafer level package [FOWLP] RDLs
- H10W 70/635: {Through-vias}
- H10W 74/016: {using moulds}
- H10W 74/117: {the substrate having spherical bumps for external connection}
- H10W 90/401: {characterised by multiple insulating or insulated package substrates, interposers or RDLs}
- H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts}
- H10W 70/654: Top-view layouts
- H10W 72/241: {Dispositions, e.g. layouts}
- H10W 72/29: Bond pads specially adapted therefor
- H10W 72/9413: {on encapsulations}
- H10W 74/00: Encapsulations, e.g. protective coatings
- H10W 74/15: on active surfaces of flip-chip devices, e.g. underfills
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor device is described having at least one semiconductor chip, the chip having an active area on a top side thereof, the active area formed at least in part of low-k material, said low-k material defining a low-k subarea of said active area; an embedding material, in which said at least one semiconductor chip is embedded, at least part of the embedding material forming a coplanar area with said active area; at least one contact area within the low-k subarea; a redistribution layer on the coplanar area, the redistribution layer connected to said contact areas; at least one first-level interconnect, located outside said low-k subarea, the first-level interconnect electrically connected to at least one of said contact areas via the redistribution layer.

## Claims

### Claim 1

A semiconductor device comprising:
at least one semiconductor chip, the chip comprising: an active area on a top side of the at least one semiconductor chip, the active area being formed at least in part of a low-k material defining a low-k sub-area of the active area;
an embedding material embedding the at least one semiconductor chip, wherein at least part of the embedding material forms a coplanar area with the active area;
at least one contact area disposed within the low-k sub-area; and
at least one interconnect, located outside the low-k sub-area, the interconnect electrically connected to the at least one contact area.

### Claim 2

(canceled)

### Claim 3 (depends on 1)

The device of claim 1, further comprising:
a redistribution layer disposed on the coplanar area, wherein the redistribution layer is electrically connected to the at least one contact area.

### Claim 4 (depends on 3)

The device of claim 3, wherein the at least one interconnect is electrically connected to the at least one contact area via the redistribution layer.

### Claim 5 (depends on 4)

The device of claim 4, further comprising:
a dielectric layer disposed on the coplanar area.

### Claim 6 (depends on 4)

The device of claim 4, further comprising:
a protection layer disposed over the low-k sub-area.

### Claim 7 (depends on 6)

The device of claim 6, wherein the protection layer is composed of one or more materials selected from the group consisting of: silicone, polyurethane, epoxy, polyimide.

### Claim 8 (depends on 6)

The device of claim 6, wherein the protection layer comprises silicone particles with one of the following fillers: air gaps, air foams, bubbles.

### Claim 9 (depends on 4)

The device of claim 4, further comprising:
a lid disposed over the active area.

### Claim 10 (depends on 9)

The device of claim 9, wherein the lid is one of a polymer lid, a metal lid and a ceramic lid.

### Claim 11 (depends on 9)

The device of claim 9, wherein the lid is glued, soldered, clamped, or bonded to the active area.

### Claim 12 (depends on 1)

The device of claim 1, wherein the at least one interconnect is located on a back side of the at least one semiconductor chip.

### Claim 13 (depends on 12)

The device of claim 12, wherein the at least one interconnect is electrically connected to the at least one contact area by at least one through-silicon-via.

### Claim 14 (depends on 13)

The device of claim 13, wherein the low-k sub-area is mechanically decoupled from the back side of the at least one chip by at least one layer of silicon.

### Claim 15 (depends on 1)

The device of claim 1, further comprising:
a substrate electrically connected to the at least one interconnect.

### Claim 16 (depends on 1)

The device of claim 1, wherein the at least one interconnect is a flip-chip bump or a copper pillar.

### Claim 17

A semiconductor device comprising:
at least one semiconductor chip, the chip comprising: an active area on a top side of the at least one semiconductor chip, the active area being formed at least in part of a low-k material defining a low-k sub-area of the active area;
an embedding material embedding the at least one semiconductor chip, wherein at least part of the embedding material forms a coplanar area with the active area;
at least one contact area disposed within the low-k sub-area;
a redistribution layer disposed on the coplanar area, wherein the redistribution layer is electrically connected to the at least one contact area;
at least one interconnect, located outside the low-k subarea, the interconnect electrically connected to the at least one contact area via the redistribution layer.

### Claim 18 (depends on 17)

The device of claim 17, further comprising:
a dielectric layer disposed on the coplanar area.

### Claim 19 (depends on 17)

The device of claim 17, further comprising:
a protection layer applied over the low-k sub-area.

### Claim 20 (depends on 19)

The device of claim 19, wherein the protection layer is composed of one or more materials selected from the group consisting of: silicone, polyurethane, epoxy, polyimide.

### Claim 21 (depends on 19)

The device of claim 19, wherein the protection layer contains silicone particles with one of the following fillers: air gaps, air foams, bubbles.

### Claim 22 (depends on 17)

The device of claim 17, further comprising:
a lid disposed over the active area.

### Claim 23 (depends on 22)

The device of claim 22, wherein the lid is one of a polymer lid, a metal lid and a ceramic lid.

### Claim 24 (depends on 22)

The device of claim 22, wherein the lid is glued, soldered, clamped, or bonded to the active area.

### Claim 25 (depends on 17)

The device of claim 17, further comprising:
a substrate electrically connected to the at least one interconnect.

### Claim 26 (depends on 17)

The device of claim 17, wherein the at least one interconnect is a flip-chip bump or a copper pillar.

### Claim 27

A method of producing a semiconductor device, comprising:
embedding a semiconductor chip, including a top side with an active area formed at least part of low-k material defining a low-k sub-area, into an embedding material;
forming a planar surface on the embedding material, the active area coplanar with the embedding material;
disposing at least one contact area within the low-k sub-area;
disposing a redistribution layer on the coplanar area, the redistribution layer electrically connected to the at least one contact area;
forming at least one interconnect outside the low-k sub-area, the at least one interconnect electrically connected to the at least one contact area within the low-k sub-area via the redistribution layer.

### Claim 28 (depends on 27)

The method of claim 27, further comprising:
depositing a dielectric layer on the coplanar area.

### Claim 29 (depends on 27)

The method of claim 27, further comprising:
depositing a protection layer over the low-k sub-area.

### Claim 30 (depends on 27)

The method of claim 27, further comprising:
disposing a lid over the low-k sub-area.

### Claim 31 (depends on 27)

The method of claim 27, further comprising:
connecting a substrate electrically with the at least one interconnect.