# US 2014/0197529 A1 · Methods of fabricating package stack structure and method of mounting package stack structure on system board

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- Number: US 2014/0197529 A1
- Document ID: US20140197529A1
- Status: Published application
- Kind: A1
- Application number: 14/196,577
- Filed: 2014-03-04
- Published: 2014-07-17
- Earliest claimed: 2010-09-27
- Assignees: Samsung Electronics Co., Ltd.
- Inventors: Sun-Kyoung Seo; Eun-Jin Choi
- Web page: https://patentgrep.com/patent/US20140197529A1

## CPC

- H10W 90/00: Package configurations
- H10W 40/43: by flowing gases, e.g. forced air cooling
- H10W 74/01: Manufacture or treatment
- H10W 74/117: {the substrate having spherical bumps for external connection}
- H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts}
- H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40)
- H10W 72/07254: {changes in dispositions}
- H10W 72/20: Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
- H10W 72/244: {relative to underlying supporting features, e.g. bond pads, RDLs or vias}
- H10W 72/247: {Dispositions of multiple bumps}
- H10W 72/248: {Top-view layouts, e.g. mirror arrays}
- H10W 72/252: {comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu}
- H10W 72/325: {Die-attach connectors having a filler embedded in a matrix}
- H10W 72/352: {comprising metals or metalloids, e.g. solders}
- H10W 72/353: {not comprising solid metals or solid metalloids, e.g. ceramics}
- H10W 72/354: {comprising polymers}
- H10W 72/5522: {comprising gold [Au]}
- H10W 72/5524: {comprising aluminium [Al]}
- H10W 72/865: {Die-attach connectors and bond wires}
- H10W 72/877: {Bump connectors and die-attach connectors}
- H10W 72/884: {Die-attach connectors and bond wires}
- H10W 74/00: Encapsulations, e.g. protective coatings
- H10W 74/10: characterised by their shape or disposition
- H10W 74/142: {the encapsulations exposing the passive side of the semiconductor body}
- H10W 74/15: on active surfaces of flip-chip devices, e.g. underfills
- H10W 90/28: the stacked chips having different sizes, e.g. chip stacks having a pyramidal shape
- H10W 90/288: {characterised by arrangements for thermal management of the stacked chips}
- H10W 90/291: {characterised by containers, encapsulations, or other housings for the stacked chips}
- H10W 90/401: {characterised by multiple insulating or insulated package substrates, interposers or RDLs}
- H10W 90/722: {between stacked chips}
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/732: {between stacked chips}
- H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/752: {between stacked chips}
- H10W 90/754: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A package stack structure includes a lower semiconductor chip on a lower package substrate having a plurality of lower via plug lands, a lower package having a lower molding compound surrounding a portion of a top surface of the lower package substrate and side surfaces of the lower semiconductor chip, an upper semiconductor chip on an upper package substrate having a plurality of upper via plug lands, an upper package having an upper molding compound covering the upper semiconductor chip, via plugs vertically penetrating the lower molding compound, the via plugs connecting the lower and upper via plug lands, respectively, and a fastening element and an air space between a top surface of the lower molding compound and a bottom surface of the upper package substrate.

## Claims

### Claim at position 1

1-20. (canceled)

### Claim 21

A package stack structure comprising:
a first package including a first semiconductor chip, a first package substrate, and a first molding compound, the first semiconductor chip disposed on the first package substrate and at least partially surrounded by the first molding compound;
a second package including a second semiconductor chip, a second package substrate, and a second molding compound, the second semiconductor chip disposed on the second package substrate and disposed in the second molding compound;
a plurality of via plugs disposed in the first molding compound for electrically connecting the first package and the second package; and
an interposing element disposed between a top surface of the first semiconductor chip and a bottom surface of the second package substrate, wherein the interposing element occupies an area smaller than the top surface of the semiconductor chip.

### Claim 22 (depends on 21)

The package stack structure of claim 21, wherein the interposing element does not overlap any side of the top surface of the semiconductor chip.

### Claim 23 (depends on 21)

The package stack structure of claim 21, wherein the interposing element does not overlap at least two corners of the top surface of the semiconductor chip.

### Claim 24 (depends on 21)

The package stack structure of claim 21, wherein the interposing element overlaps at least one side of the top surface of the semiconductor chip.

### Claim 25 (depends on 21)

The package stack structure of claim 21, wherein the interposing element is thermally conductive.

### Claim 26 (depends on 21)

The package stack structure of claim 21, wherein the interposing element is an epoxy resin.

### Claim 27 (depends on 21)

The package stack structure of claim 21, wherein the interposing element is positioned to form an air space between the first package and the second package, the air space providing an air path to outer areas of the package stack structure.

### Claim 28 (depends on 21)

The package stack structure of claim 21, wherein the interposing element includes organic polymer particles.

### Claim 29 (depends on 21)

The package stack structure of claim 21, wherein the interposing element includes metallic particles.

### Claim 30

A package stack structure comprising:
a first package including a first semiconductor chip, a first package substrate, and a first molding compound, The first semiconductor chip disposed on the first package substrate and at least partially surrounded by the first molding compound;
a second package including a second semiconductor chip, a second package substrate, and a second molding compound, The second semiconductor chip disposed on the second package substrate and disposed in the second molding compound;
a plurality of via plugs disposed in the first molding compound for electrically connecting the first package and the second package; and
an interposing element disposed between a top surface of the first semiconductor chip and a bottom surface of the second package substrate, wherein the interposing element overlaps at least one side of the top surface of the semiconductor chip.

### Claim 31 (depends on 30)

The package stack structure of claim 30, wherein the interposing element occupies an area smaller than the top surface of the semiconductor chip.

### Claim 32 (depends on 30)

The package stack structure of claim 30, wherein the interposing element occupies an area greater than the top surface of the semiconductor chip.

### Claim 33 (depends on 30)

The package stack structure of claim 30, wherein the interposing element does not overlap at least two corners of the top surface of the semiconductor chip.

### Claim 34 (depends on 30)

The package stack structure of claim 30, wherein the interposing element is thermally conductive.

### Claim 35 (depends on 30)

The package stack structure of claim 30, wherein the interposing element is an epoxy resin.

### Claim 36 (depends on 30)

The package stack structure of claim 30, wherein the interposing element is positioned to form an air space between the first package and the second package, the air space providing an air path to outer areas of the package stack structure.

### Claim 37 (depends on 30)

The package stack structure of claim 30, wherein the interposing element includes organic polymer particles.

### Claim 38 (depends on 30)

The package stack structure of claim 30, wherein the interposing element includes metallic particles.

### Claim 39

A package stack structure comprising:
a first package including a first semiconductor chip, a first package substrate, and a first molding compound, The first semiconductor chip disposed on the first package substrate and at least partially surrounded by the first molding compound;
a second package including a second semiconductor chip, a second package substrate, and a second molding compound, The second semiconductor chip disposed on the second package substrate and disposed in the second molding compound;
a plurality of via plugs disposed in the first molding compound for electrically connecting the first package and the second package; and
an interposing element disposed between a top surface of the first semiconductor chip and a bottom surface of the second package substrate, wherein the interposing element overlaps at least two sides of the top surface of the semiconductor chip.