# US 2014/0197527 A1 · Chip arrangement and a method for manufacturing a chip arrangement > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2014/0197527 A1 - Document ID: US20140197527A1 - Status: Published application - Kind: A1 - Application number: 13/742,455 - Filed: 2013-01-16 - Published: 2014-07-17 - Earliest claimed: 2013-01-16 - Assignees: Infineon Technologies AG - Applicants: Infineon Technologies AG - Inventors: Manfred Mengel; Joachim Mahler; Khalil Hosseini; Franz-Peter Kalz - Web page: https://patentgrep.com/patent/US20140197527A1 ## CPC - H10W 99/00: Subject matter not provided for in other groups of this subclass - H10D 84/01: Manufacture or treatment - H10W 40/255: {having a laminate or multilayered structure, e.g. direct bond copper [DBC] ceramic substrates} - H10W 40/259: {Ceramics or glasses (H10W40/254, H10W40/257, H10W40/255, H10W40/251, H10W40/253 take precedence)} - H10W 70/041: {Connecting or disconnecting interconnections to or from leadframes, e.g. connecting bond wires or bumps} - H10W 70/458: {of insulating layers on leadframes} - H10W 70/481: {for devices being provided for in groups H10D8/00 - H10D48/00} - H10W 72/0113: {Apparatus for manufacturing die-attach connectors} - H10W 72/013: {of die-attach connectors} - H10W 74/01: Manufacture or treatment - H10W 90/00: Package configurations - H10W 90/811: {Multiple chips on leadframes} - H10W 72/073: {of die-attach connectors} - H10W 72/075: {of bond wires} - H10W 72/536: {the connected ends being ball-shaped} - H10W 72/5363: {the connected ends being wedge-shaped} - H10W 72/5475: {multiple bond wires connected to common bond pads at both ends of the wires} - H10W 72/884: {Die-attach connectors and bond wires} - H10W 74/00: Encapsulations, e.g. protective coatings - H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL} - H10W 90/736: {between a chip and a stacked lead frame, conducting package substrate or heat sink} - H10W 90/752: {between stacked chips} - H10W 90/753: {between laterally-adjacent chips} - H10W 90/756: {between a chip and a stacked lead frame, conducting package substrate or heat sink} - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES ## Abstract A chip arrangement is provided, the chip arrangement, including a carrier; a first chip electrically connected to the carrier; a ceramic layer disposed over the carrier; and a second chip disposed over the ceramic layer; wherein the ceramic layer has a porosity in the range from about 3% to about 70%. ## Claims ### Claim 1 A chip arrangement, comprising: a carrier; a first chip electrically connected to the carrier; a ceramic layer disposed over the carrier; and a second chip disposed over the ceramic layer; wherein the ceramic layer has a porosity in the range from 3% to 70%. ### Claim 2 (depends on 1) The chip arrangement according to claim 1, wherein the first chip comprises a power semiconductor chip. ### Claim 3 (depends on 2) The chip arrangement according to claim 2, wherein the power semiconductor chip comprises at least one power semiconductor device from the group consisting of: a power transistor, a power MOS transistor, a power bipolar transistor, a power field effect transistor, a power insulated gate bipolar transistor, a thyristor, a MOS controlled thyristors, a silicon controlled rectifier, a power schottky diode, a silicon carbide diode, a gallium nitride device. ### Claim 4 (depends on 1) The chip arrangement according to claim 1, wherein the second chip comprises a semiconductor logic chip or a semiconductor memory chip. ### Claim 5 (depends on 4) The chip arrangement according to claim 4, wherein the semiconductor logic chip comprises a semiconductor logic device from the group consisting of: an application specific integrated circuit, a driver, a controller, and a sensor. ### Claim 6 (depends on 1) The chip arrangement according to claim 1, wherein a first chip side is electrically connected to the carrier via an electrically conductive medium. ### Claim 7 (depends on 6) The chip arrangement according to claim 6, wherein the electrically conductive medium comprises at least one from the following group of materials, the group consisting of: a solder, a soft solder, a diffusion solder, a paste, a nanopaste, an adhesive, an electrically conductive adhesive and a thermally conductive adhesive. ### Claim 8 (depends on 1) The chip arrangement according to claim 1, wherein the ceramic layer is adhered directly on the carrier by means of an adhesive material. ### Claim 9 (depends on 1) The chip arrangement according to claim 1, wherein the ceramic layer comprises at least one of an electrically insulating material and a thermally conducting material. ### Claim 10 (depends on 1) The chip arrangement according to claim 1, wherein the ceramic layer comprises one or more particles, the one or more particles comprising at least one from the following group of materials, the group of materials consisting of: aluminum oxide, aluminum nitride, silicon dioxide, silicon nitride, silicon carbide, titanium dioxide, titanium nitride, zirconium dioxide, boron nitride, boron carbide. ### Claim 11 (depends on 10) The chip arrangement according to claim 10, wherein the ceramic layer further comprises a filler material, the filler material comprising at least one from the following group of materials, the group of materials consisting of: an organic material, plastic, epoxy, polyimide, thermoset, polyacrylate, silicone and silica. ### Claim 12 (depends on 1) The chip arrangement according to claim 1, wherein the carrier comprises an electrically conductive material. ### Claim 13 (depends on 1) The chip arrangement according to claim 1, wherein the carrier comprises a lead frame, the lead frame comprising at least one from the following group of materials, the group of materials consisting of: copper, nickel, iron, silver, gold, palladium, phosphorous, copper alloy, nickel alloy, iron alloy, silver alloy, gold alloy, palladium alloy, phosphorous alloy. ### Claim 14 (depends on 1) The chip arrangement according to claim 1, further comprising an encapsulation material disposed over the carrier, wherein the encapsulation material at least partially surrounds the first chip and the second chip, and one or more lateral sides of the carrier. ### Claim 15 (depends on 1) The chip arrangement according to claim 1, further comprising at least one electrically conductive layer formed at least one of over and under the ceramic layer. ### Claim 16 (depends on 1) The chip arrangement according to claim 1, wherein the at least one electrically conductive layer comprises at least one from the following group of materials, the group of materials consisting of: tin, lead, silver, copper, nickel, palladium, zinc, aluminum, gold, antimony, inorganic elements and organic elements. ### Claim 17 A method for manufacturing a chip arrangement, the method comprising: electrically connecting a first chip to a carrier; disposing a ceramic layer having a porosity in the range from 3% to 70% over the carrier; and disposing a second chip over the ceramic layer. ### Claim 18 (depends on 17) The method according to claim 17, comprising adhering the ceramic layer directly on the carrier by means of an adhesive material. ### Claim 19 (depends on 17) The method according to claim 17, wherein the ceramic layer comprises at least one of an electrically insulating material and a thermally conducting material. ### Claim 20 (depends on 17) The method according to claim 17, wherein the ceramic layer comprises one or more particles, the one or more particles comprising at least one from the following group of materials, the group of materials consisting of: aluminum oxide, aluminum nitride, silicon dioxide, silicon nitride, silicon carbide, titanium dioxide, titanium nitride, zirconium dioxide, boron nitride, boron carbide. ### Claim 21 (depends on 17) The method according to claim 17, wherein the carrier comprises a lead frame, the lead frame comprising at least one from the following group of materials, the group of materials consisting of: copper, nickel, iron, silver, gold, palladium, phosphorous, copper alloy, nickel alloy, iron alloy, silver alloy, gold alloy, palladium alloy, phosphorous alloy. ### Claim 22 (depends on 17) The method according to claim 17, further comprising disposing an encapsulation material over the carrier, wherein the encapsulation material at least partially surrounds the first chip and the second chip, and one or more lateral sides of the carrier. ### Claim 23 (depends on 17) The method according to claim 17, further comprising forming at least one electrically conductive layer over the carrier before depositing the ceramic layer; and depositing the ceramic layer over the at least one electrically conductive layer. ### Claim 24 (depends on 17) The method according to claim 17, further comprising forming at least one electrically conductive layer over the ceramic layer; and forming the second chip over the least one electrically conductive layer. ### Claim 25 (depends on 17) The method according to claim 17, comprising electrically connecting the first chip to the carrier via an electrically conductive medium comprising at least one material from the following group of materials, the group consisting of: a solder, a soft solder, a diffusion solder, a paste, a nanopaste, an adhesive, an electrically conductive adhesive, a thermally conductive adhesive. ### Claim 26 (depends on 17) The method according to claim 17, wherein the first chip comprises a power semiconductor chip. ### Claim 27 (depends on 17) The method according to claim 17, wherein the second chip comprises a semiconductor logic chip or a semiconductor memory chip.