# US 2014/0197526 A1 · Semiconductor device assembly with through-package interconnect and associated systems, devices, and methods

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- Number: US 2014/0197526 A1
- Document ID: US20140197526A1
- Status: Published application
- Kind: A1
- Application number: 13/739,331
- Filed: 2013-01-11
- Published: 2014-07-17
- Earliest claimed: 2013-01-11
- Assignees: Micron Technology, Inc.
- Applicants: Micron Technology, Inc.
- Inventors: Chan Yoo; Todd O. Bolken
- Web page: https://patentgrep.com/patent/US20140197526A1

## CPC

- H10W 90/00: Package configurations
- H10D 84/01: Manufacture or treatment
- H10W 70/40: Leadframes
- H10W 72/20: Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
- H10W 74/01: Manufacture or treatment
- H10W 74/014: {using batch processing}
- H10W 74/016: {using moulds}
- H10W 74/017: {Auxiliary layers for moulds, e.g. release layers or layers preventing residue}
- H10W 74/117: {the substrate having spherical bumps for external connection}
- H10W 74/127: {characterised by arrangements for sealing or adhesion}
- H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40)
- H10W 70/656: Fan-in layouts
- H10W 72/01235: {by plating, e.g. electroless plating or electroplating}
- H10W 72/019: {of bond pads}
- H10W 72/0198: {batch processes}
- H10W 72/072: {of bump connectors}
- H10W 72/07253: {changes in shapes}
- H10W 72/073: {of die-attach connectors}
- H10W 72/075: {of bond wires}
- H10W 72/231: {Shapes}
- H10W 72/232: {Plan-view shape, i.e. in top view}
- H10W 72/234: {Cross-sectional shape, i.e. in side view}
- H10W 72/237: {Multiple bump connectors having different shapes}
- H10W 72/241: {Dispositions, e.g. layouts}
- H10W 72/244: {relative to underlying supporting features, e.g. bond pads, RDLs or vias}
- H10W 72/252: {comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu}
- H10W 72/281: {Auxiliary members}
- H10W 72/29: Bond pads specially adapted therefor
- H10W 72/354: {comprising polymers}
- H10W 72/5445: {being orthogonal to a side surface of the chip, e.g. parallel arrangements}
- H10W 72/551: {Materials of bond wires}
- H10W 72/59: Bond pads specially adapted therefor
- H10W 72/859: {Bump connectors and bond wires}
- H10W 72/865: {Die-attach connectors and bond wires}
- H10W 72/877: {Bump connectors and die-attach connectors}
- H10W 72/884: {Die-attach connectors and bond wires}
- H10W 72/90: Bond pads, in general
- H10W 72/9415: {relative to the surface, e.g. recessed, protruding}
- H10W 72/9445: {Top-view layouts, e.g. mirror arrays}
- H10W 72/952: {comprising metals or metalloids, e.g. PbSn, Ag or Cu}
- H10W 74/00: Encapsulations, e.g. protective coatings
- H10W 90/26: the stacked chips being of the same size without any chips being laterally offset, e.g. chip stacks having a rectangular shape
- H10W 90/721: {of bump connectors}
- H10W 90/722: {between stacked chips}
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/732: {between stacked chips}
- H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/754: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

Methods for making semiconductor devices are disclosed herein. A method configured in accordance with a particular embodiment includes forming a spacer material on an encapsulant such that the encapsulant separates the spacer material from an active surface of a semiconductor device and at least one interconnect projecting away from the active surface. The method further includes molding the encapsulant such that at least a portion of the interconnect extends through the encapsulant and into the spacer material. The interconnect can include a contact surface that is substantially co-planar with the active surface of the semiconductor device for providing an electrical connection with the semiconductor device.

## Claims

### Claim 1

A method for manufacturing a semiconductor device assembly, comprising:
forming a spacer material on an encapsulant, wherein the encapsulant separates the spacer material from an active surface of a semiconductor device and at least one interconnect projecting away from the active surface; and
molding the encapsulant such that at least a portion of the interconnect extends through the encapsulant and into the spacer material, wherein the interconnect includes a generally planar surface that is substantially co-planar with the active surface of the semiconductor device.

### Claim 2 (depends on 1)

The method of claim 1, further comprising:
forming a passivation material between the active surface of the semiconductor device and the encapsulant; and
wherein forming the interconnect,
includes forming a bond pad on the passivation material; and
plating a conductive material on the bond pad.

### Claim 3 (depends on 2)

The method of claim 2 wherein plating the conductive material on the bond pad comprises forming a conductive pillar having a projection height greater than a thickness of the encapsulant between the spacer material and the passivation material.

### Claim 4 (depends on 2)

The method of claim 2, further comprising:
forming a redistribution network on the passivation material, wherein the redistribution network includes the bond pad and at least one conductive trace coupled to the bond pad; and
forming a wirebond electrically coupled to the bond pad via the conductive trace of the redistribution network.

### Claim 5 (depends on 1)

The method of claim 1 wherein the active surface of the semiconductor device comprises a bond pad, and wherein the method further comprises forming the interconnect by electroplating a conductive material onto the bond pad.

### Claim 6 (depends on 1)

The method of claim 1 wherein molding the encapsulant comprises forming a casing that at least partially encapsulates the semiconductor device with the encapsulant.

### Claim 7 (depends on 1)

The method of claim 1 wherein the semiconductor device comprises a first semiconductor die having an active surface that includes the active surface of the semiconductor device, and wherein the method further comprises:
attaching a second semiconductor die to a support substrate;
attaching the first semiconductor die to the second semiconductor die; and
wirebonding one or more first bond pads at the active surface of the first semiconductor die to one or more second bond pads at the support substrate.

### Claim 8 (depends on 1)

The method of claim 1 wherein the semiconductor device and the encapsulant form at least a portion of a first semiconductor device package, and wherein the method further comprises:
attaching a second semiconductor device package to the first semiconductor device package, wherein the second semiconductor device package includes a contact electrically coupled to the first device package via the portion of the interconnect that extends through the encapsulant.

### Claim 9 (depends on 8)

The method of claim 8 wherein the portion of the interconnect that extends through the encapsulant comprises a first interconnect, and wherein attaching the second semiconductor device package to the first semiconductor device package comprises forming a second interconnect at the first interconnect, wherein the second interconnect fits within a planform shape defined by the first semiconductor device package.

### Claim 10 (depends on 8)

The method of claim 8 wherein attaching the second semiconductor device package to the first semiconductor device package comprises forming a solder ball at the portion of the interconnect that extends through the encapsulant.

### Claim 11 (depends on 8)

The method of claim 8, further comprising forming a redistribution network at the active surface of the semiconductor device of the first semiconductor device package, wherein the interconnect electrically couples the second semiconductor device with the redistribution network.

### Claim 12 (depends on 8)

The method of claim 8 wherein the semiconductor device of the first semiconductor device package comprises a semiconductor die having an active surface that includes the active surface of the semiconductor device, and wherein the method further comprises:
forming a redistribution network at the active surface of the semiconductor die of the first semiconductor device package, wherein the redistribution network includes the interconnect, and wherein the interconnect electrically couples the second semiconductor device to the redistribution network without providing an electrical coupling between the second semiconductor device and the semiconductor die of the first semiconductor device package.

### Claim 13

A method of manufacturing a semiconductor device package, the method comprising:
receiving a semiconductor device in a mold cavity, wherein the semiconductor device includes a conductive feature at an active surface of the semiconductor device, wherein the conductive feature has a contact surface and straight sidewalls that are transverse to the contact surface and project away from the active surface of the semiconductor device by a distance;
disposing a spacer between a molding surface in the mold cavity and the active surface of the semiconductor device;
flowing an encapsulant in the mold cavity; and
moving the molding surface and the active surface of the semiconductor device towards one another to contact the spacer with at least a portion of the conductive feature

### Claim 14 (depends on 13)

The method of claim 13 wherein flowing the encapsulant comprises injecting the encapsulant in the mold cavity.

### Claim 15 (depends on 13)

The method of claim 13 wherein disposing the spacer comprises disposing a spacer material on the molding surface in the mold cavity.

### Claim 16 (depends on 13)

The method of claim 13 wherein disposing the spacer comprises laminating a spacer material on the molding surface of the mold.

### Claim 17 (depends on 13)

The method of claim 13 wherein the encapsulant is between the molding surface of the mold cavity and the active surface of the semiconductor device, and wherein disposing the spacer comprises disposing a spacer material on an active surface of the encapsulant.

### Claim 18 (depends on 13)

The method of claim 13 wherein pressing the molding surface and the active surface of the semiconductor device towards one another comprises pressing a plate of a molding apparatus and the active surface of the semiconductor device towards one another.

### Claim 19

A method of manufacturing a semiconductor device assembly, comprising:
at least partially encapsulating a semiconductor device and a feature attached to the semiconductor device with a first material, wherein the feature includes a plated material;
forming a second material that covers an outer surface of the first material; and contacting the second material with at least a portion of the feature.

### Claim 20 (depends on 19)

The method of claim 19 wherein contacting the second material with the portion of the feature comprises pressing the portion of the feature through the first material and penetrating the portion of the feature into the second material

### Claim 21 (depends on 19)

The method of claim 19, further comprising:
forming a semiconductor device package that includes the semiconductor device, the feature, and at least a portion of the first material; and
forming an electrical connection with the semiconductor device package via the feature.

### Claim 22 (depends on 19)

The method of claim 19, further comprising forming the feature by one or more processes that include forming a conductive standoff structure at surface of the semiconductor die.

### Claim at position 23

23-34. (canceled)