# US 2014/0197522 A1 · Hybrid conductor through-silicon-via for power distribution and signal transmission

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- Number: US 2014/0197522 A1
- Document ID: US20140197522A1
- Status: Published application
- Kind: A1
- Application number: 13/741,947
- Filed: 2013-01-15
- Published: 2014-07-17
- Earliest claimed: 2013-01-15
- Assignees: International Business Machines Corporation
- Inventors: Xiaoxiong Gu; Michael Mcallister
- Web page: https://patentgrep.com/patent/US20140197522A1

## CPC

- H10W 20/023: {the interconnections being through-semiconductor vias}
- H10W 20/20: Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
- H10W 20/212: {Top-view shapes or dispositions, e.g. top-view layouts of the vias}
- H10W 20/2125: {Top-view shapes}
- H10W 20/2128: {Coaxial through-semiconductor vias}
- H10W 20/423: {Shielding layers}
- H10W 20/427: {Power or ground buses}
- H10W 20/481: {on the rear surfaces of the wafers or substrates}
- H10W 42/271: {the arrangements being between stacked chips}
- H10W 72/0198: {batch processes}
- H10W 72/07254: {changes in dispositions}
- H10W 72/244: {relative to underlying supporting features, e.g. bond pads, RDLs or vias}
- H10W 72/247: {Dispositions of multiple bumps}
- H10W 72/248: {Top-view layouts, e.g. mirror arrays}
- H10W 90/00: Package configurations
- H10W 90/26: the stacked chips being of the same size without any chips being laterally offset, e.g. chip stacks having a rectangular shape
- H10W 90/297: {characterised by the through-semiconductor vias [TSVs] in the stacked chips}
- H10W 90/722: {between stacked chips}
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A method of providing signal, power and ground through a through-silicon-via (TSV), and an integrated circuit chip having a TSV that simultaneously provides signal, power and ground. In one embodiment, the method comprises forming a TSV through a semiconductor substrate, including forming a via in the substrate; and forming a multitude of conductive bars in the via. The multitude of conductive bars include at least one signal bar, at least one power bar, and at least one ground bar. The method further comprises connecting the at least one power bar to a power voltage source to apply power through the TSV; connecting the at least one ground bar to a ground voltage; and connecting the at least one signal bar to a source of an electronic signal to conduct the signal through the TSV and to form a hybrid power-ground-signal TSV in the substrate.

## Claims

### Claim at position 1

1-10. (canceled)

### Claim 11

An integrated circuit comprising:
a semiconductor substrate;
a through-the-substrate via (TSV) formed in and extending through the semiconductor substrate and including an outside insulating layer, at least one signal bar, at least one power bar, and at least one ground bar; and
a series of overlapping wiring layers to connect the at least one signal bar to a signal source, the at least one power bar to a power source, and the at least one ground bar to a ground, to combine power, ground and signal in one TSV, the series of overlapping wiring layers including
a power layer connected to the at least one power bar and extending outside the TSV for connecting the at least one power bar to a power voltage source to apply power through the TSV;
a ground layer connected to the at least one ground bar and extending outside the TSV for connecting the at least one ground bar to a ground voltage; and
a signal layer connected to the at least one signal bar and extending outside the TSV for connecting the at least one signal bar to a source of an electronic signal to conduct the signal through the TSV;
wherein the TSV forms a hybrid power-ground-signal TSV in the substrate.

### Claim 12 (depends on 11)

The integrated circuit according to claim 11, wherein the at least one signal bar is located between the at least one power bar and the at least one ground bars whereby the at least one power bar and the at least one ground bar form an electric shield for the at least one signal bar.

### Claim 13 (depends on 11)

The integrated circuit according to claim 11, wherein the signal bar is located substantially mid-way between the at least one power bar and the at least one ground bar.

### Claim 14 (depends on 11)

The integrated circuit according to claim 11, further comprising a second signal bar between the at least one power bar and the at least one ground bar.

### Claim 15 (depends on 11)

The integrated circuit according to claim 11, further comprising:
a plurality of additional TSVs through the semiconductor structure, each of the additional TSVs including a via in the substrate, and a multitude of conductor bars in the via, said multitude of conductor bars including at least one signal bar, at least one power bar, and at least one ground bar; and
wherein different ones of the TSVs are programmed for different uses, whereby the TSVs provide multiple capabilities in a limited number of TSV structures.

### Claim 16

An article of manufacture comprising:
at least one tangible computer readable medium having a data structure tangible embodied thereon and defining circuitry for instantiation on a semiconductor die, the data structure comprising data representing:
a through-the-substrate via (TSV) formed in and extending through the semiconductor die and including an outside insulating layer, at least one signal bar, at least one power bar, and at least one ground bar; and
a series of overlapping wiring layers to connect the at least one signal bar to a signal source, the at least one power bar to a power source, and the at least one ground bar to a ground, to combine power, ground and signal in one TSV, the series of overlapping wiring layers including
a power layer connected to the at least one power bar and extending outside the TSV for connecting the at least one power bar to a power voltage source to apply power through the TSV;
a ground layer connected to the at least one ground bar and extending outside the TSV for connecting the at least one ground bar to a ground voltage; and
a signal layer connected to the at least one signal bar and extending outside the TSV for connecting the at least one signal bar to a source of an electronic signal to conduct the signal through the TSV.

### Claim 17 (depends on 16)

The article of manufacture according to claim 16, wherein the at least one signal bar is located between the at least one power bar and the at least one ground bars whereby the at least one power bar and the at least one ground bar form an electric shield for the at least one signal bar.

### Claim 18 (depends on 16)

The article of manufacture according to claim 16, wherein the signal bar is located substantially mid-way between the at least one power bar and the at least one ground bar.

### Claim 19 (depends on 16)

The article of manufacture according to claim 16, wherein said data further represents a second signal bar between the at least one power bar and the at least one ground bar.

### Claim 20 (depends on 16)

The article of manufacture according to claim 16, wherein said data further represents a plurality of additional TSVs through the semiconductor structure, each of the additional TSVs including a via in the substrate, and a multitude of conductor bars in the via, said multitude of conductor bars including at least one signal bar, at least one power bar, and at least one ground bar; and wherein different ones of the TSVs are programmed for different uses, whereby the TSVs provide multiple capabilities in a limited number of TSV structures.

### Claim 21 (depends on 11)

The integrated circuit according to claim 11, wherein each of the at least one signal bar, the at least one power bar, and the at least one ground bar has a rectangle shape, and are substantially parallel to each other.