# US 2014/0197520 A1 · Resistor and resistor fabrication for semiconductor devices > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2014/0197520 A1 - Document ID: US20140197520A1 - Status: Published application - Kind: A1 - Application number: 13/743,434 - Filed: 2013-01-17 - Published: 2014-07-17 - Earliest claimed: 2013-01-17 - Assignees: QUALCOMM Incorporated - Applicants: Qualcomm Incorporated - Inventors: Jihong Choi; John J. Zhu; Bin Yang; Giridhar Nallapati; PR Chidambaram - Web page: https://patentgrep.com/patent/US20140197520A1 ## CPC - H10D 1/47: Resistors having no potential barriers - H10D 1/474: {comprising refractory metals, transition metals, noble metals, metal compounds or metal alloys, e.g. silicides} - H10D 84/811: {Combinations of field-effect devices and one or more diodes, capacitors or resistors} - H10D 84/817: {Combinations of field-effect devices and resistors only} - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES ## Abstract In a particular embodiment, a method includes removing a first portion of an optical planarization layer using a lithographic mask to expose a region of the optical planarization layer. A resistive layer is formed at least partially within the region. The method further includes removing at least a second portion of the optical planarization layer and at least a third portion of the resistive layer to form a resistor. ## Claims ### Claim 1 A method comprising: removing a first portion of an optical planarization layer using a lithographic mask to expose a region of the optical planarization layer; forming a resistive layer at least partially within the region; and removing at least a second portion of the optical planarization layer and at least a third portion of the resistive layer to form a resistor. ### Claim 2 (depends on 1) The method of claim 1, wherein the resistor is formed according to a single-mask fabrication technique, and wherein the second portion and the third portion are removed according to a lift-off fabrication technique. ### Claim 3 (depends on 1) The method of claim 1, further comprising: forming an interconnect layer of an integrated circuit; and forming the optical planarization layer on the interconnect layer. ### Claim 4 (depends on 3) The method of claim 3, wherein the interconnect layer is a local interconnect layer formed during a middle-of-line (MOL) fabrication stage of fabricating the integrated circuit. ### Claim 5 (depends on 4) The method of claim 4, wherein the interconnect layer is formed on a semiconductor substrate. ### Claim 6 (depends on 1) The method of claim 1, wherein the resistor is a high-resistance resistor having a shed resistance of between 400 to 700 ohms. ### Claim 7 (depends on 1) The method of claim 1, further comprising depositing a capping layer on the resistor. ### Claim 8 (depends on 1) The method of claim 1, wherein the resistive layer is formed according to a physical vapor deposition (PVD)fabrication technique, a chemical vapor deposition (CVD) fabrication technique, a plasma-enhanced chemical vapor deposition (PECVD) fabrication technique, or a combination thereof. ### Claim 9 (depends on 1) The method of claim 1, wherein removing the first portion of the optical planarization layer, forming the resistive layer, and removing the second portion and the third portion are initiated by a processor integrated into an electronic device. ### Claim 10 (depends on 1) An apparatus comprising: a semiconductor device formed according to the method of claim 1. ### Claim 11 (depends on 10) The apparatus of claim 10, integrated in at least one semiconductor die. ### Claim 12 (depends on 10) The apparatus of claim 10, further comprising a device selected from the group of a set top box, a music player, a video player, an entertainment unit, a navigation device, a communications device, a personal digital assistant (PDA), a fixed location data unit, and a computer, into which the semiconductor device is integrated. ### Claim 13 A method comprising: a first step for removing a first portion of an optical planarization layer using a lithographic mask to expose a region; a second step for forming a resistive layer at least partially within the region; and a third step for removing at least a second portion of the optical planarization layer and at least a third portion of the resistive layer to form a resistor. ### Claim 14 (depends on 13) The method of claim 13, wherein the first step, the second step, and the third step are initiated by a processor integrated into an electronic device. ### Claim 15 (depends on 1) A method comprising: receiving a data file including design information corresponding to a semiconductor device; and fabricating the semiconductor device according to the design information, wherein the semiconductor device includes a resistor formed according to the method of claim 1. ### Claim 16 (depends on 15) The method of claim 15, wherein the data file has a GDSII format. ### Claim 17 (depends on 1) A method comprising: receiving design information including physical positioning information of a packaged semiconductor device on a circuit board, the packaged semiconductor device including a semiconductor device that includes a resistor formed according to the method of claim 1; and transforming the design information to generate a data file. ### Claim 18 (depends on 17) The method of claim 17, wherein the data file has a GERBER format. ### Claim 19 (depends on 1) A method comprising: receiving a data file including design information including physical positioning information of a packaged semiconductor device on a circuit board; and manufacturing the circuit board, the circuit board configured to receive the packaged semiconductor device according to the design information, wherein the packaged semiconductor device includes a semiconductor device that includes a resistor formed according to the method of claim 1. ### Claim 20 (depends on 19) The method of claim 19, wherein the data file has a GERBER format. ### Claim 21 (depends on 19) The method of claim 19, further comprising integrating the circuit board into a device selected from the group of a set top box, a music player, a video player, an entertainment unit, a navigation device, a communications device, a personal digital assistant (PDA), a fixed location data unit, and a computer. ### Claim 22 (depends on 1) A non-transitory computer-readable medium storing instructions executable by a computer to initiate the method of claim 1. ### Claim 23 (depends on 1) An apparatus comprising: a first semiconductor device that includes a resistor formed according to the method of claim 1; and means for electrically coupling the first semiconductor device to at least a second semiconductor device. ### Claim 24 (depends on 23) The apparatus of claim 23, wherein the means for electrically coupling the first semiconductor device to at least the second semiconductor device comprises a printed circuit hoard (PCB).