# US 2014/0197519 A1 · Mim capacitor and mim capacitor fabrication for semiconductor devices

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- Number: US 2014/0197519 A1
- Document ID: US20140197519A1
- Status: Published application
- Kind: A1
- Application number: 13/743,388
- Filed: 2013-01-17
- Published: 2014-07-17
- Earliest claimed: 2013-01-17
- Assignees: QUALCOMM Incorporated
- Applicants: Qualcomm Incorporated
- Inventors: Jihong Choi; John J. Zhu; PR Chidambaram; Bin Yang; Lixin Ge
- Web page: https://patentgrep.com/patent/US20140197519A1

## CPC

- H10D 1/043: {using patterning processes to form electrode extensions, e.g. etching}
- H10D 1/716: {having vertical extensions}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

In a particular embodiment, a method of forming a metal-insulator-metal (MIM) capacitor includes removing, using a lithographic mask, a first portion of an optical planarization layer to expose a region in which the MIM capacitor is to be formed. A second portion of an insulating layer is formed on a first conductive layer that is formed on a plurality of trench surfaces within the region. The method further includes removing at least a third portion of the insulating layer according to a lift-off technique.

## Claims

### Claim 1

A method of forming a metal-insulator-metal (MIM) capacitor, the method comprising:
using a lithographic mask, removing a first portion of an optical planarization layer to expose a region in which the MIM capacitor is to be formed;
forming a second portion of an insulating layer on a first conductive layer that is formed on a plurality of trench surfaces within the region; and
removing at least a third portion of the insulating layer according to a lift-off technique.

### Claim 2 (depends on 1)

The method of claim 1, wherein the MIM capacitor is formed according to a single-mask technique that utilizes the lithographic mask.

### Claim 3 (depends on 1)

The method of claim 1, wherein the first conductive layer corresponds to a bottom electrode of the MIM capacitor, and further comprising:
forming a second conductive layer on the insulating layer, and
chemical-mechanical planarizing the second conductive layer.

### Claim 4 (depends on 3)

The method of claim 3, wherein the second conductive layer is formed using a copper seed deposition technique, an electroplating technique, or a combination thereof.

### Claim 5 (depends on 1)

The method of claim 1, further comprising:
forming the plurality of trench surfaces and the first conductive layer on the plurality of trench surfaces according to a dual damascene technique;
forming the optical planarization layer on the first conductive layer; and
applying the lithographic mask on at least a fourth portion of the optical planarization layer.

### Claim 6 (depends on 1)

The method of claim 1, wherein the insulating layer comprises material associated with a high dielectric constant.

### Claim 7 (depends on 1)

The method of claim 1, wherein the third portion of the insulating layer and a fourth portion of the optical planarization layer are removed according to a metal lift-off process.

### Claim 8 (depends on 1)

The method of claim 1, further comprising forming an interconnect layer above and connected to the MIM capacitor, wherein the interconnect layer includes a first via coupled to a first substantially T-shaped device and further includes a second via coupled to a second substantially T-shaped device, wherein at least a third substantially T-shaped device is coupled between the first substantially T-shaped device and the second substantially T-shaped device.

### Claim 9 (depends on 1)

The method of claim 1, wherein removing a first portion, forming the second portion, and removing the third portion are initiated by a processor integrated into an electronic device.

### Claim 10 (depends on 1)

An apparatus comprising:
a semiconductor device formed according to the method of claim 1.

### Claim 11 (depends on 10)

The apparatus of claim 10, integrated in at least one semiconductor die.

### Claim 12 (depends on 10)

The apparatus of claim 10, further comprising a device selected from the group of a set top box, a music player, a video player, an entertainment unit, a navigation device, a communications device, a personal digital assistant (PDA), a fixed location data unit, and a computer, into which the semiconductor device is integrated.

### Claim 13

A method of forming a metal-insulator-metal (MIM) capacitor, the method comprising:
a first step for removing, using a lithographic mask, a first portion of an optical planarization layer to expose a region in which the MIM capacitor is to be formed;
a second step for forming a second portion of an insulating layer on a first conductive layer that is formed on a plurality of trench surfaces within the region; and
a third step for removing at least a third portion of the insulating layer according to a lift-off technique.

### Claim 14 (depends on 13)

The method of claim 13, wherein the first step, the second step, and the third step are initiated by a processor integrated into an electronic device.

### Claim 15 (depends on 1)

A method comprising:
receiving a data file including design information corresponding to a semiconductor device; and
fabricating the semiconductor device according to the design information, wherein the semiconductor device includes a MIM capacitor formed according to the method of claim 1.

### Claim 16 (depends on 15)

The method of claim 15, wherein the data file has a GDSII format.

### Claim 17 (depends on 1)

A method comprising:
receiving design information including physical positioning information of a packaged semiconductor device on a circuit board, the packaged semiconductor device including a MIM capacitor formed according to the method of claim 1; and
transforming the design information to generate a data file.

### Claim 18 (depends on 17)

The method of claim 17, wherein the data file has a GERBER format.

### Claim 19 (depends on 1)

A method comprising:
receiving a data file including design information including physical positioning information of a packaged semiconductor device on a circuit board; and
manufacturing the circuit board, the circuit board configured to receive the packaged semiconductor device according to the design information, wherein the packaged semiconductor device includes a MIM capacitor formed according to the method of claim 1.

### Claim 20 (depends on 19)

The method of claim 19, wherein the data file has a GERBER format.

### Claim 21 (depends on 19)

The method of claim 19, further comprising integrating the circuit board into a device selected from the group of a set top box, a music player, a video player, an entertainment unit, a navigation device, a communications device, a personal digital assistant (PDA), a fixed location data unit, and a computer.

### Claim 22 (depends on 1)

A non-transitory computer-readable medium storing instructions executable by a computer to perform the method of claim 1.

### Claim 23 (depends on 1)

An apparatus comprising:
a first semiconductor device that includes a MIM capacitor formed according to the method of claim 1; and
means for electrically coupling the first semiconductor device to at least a second semiconductor device.

### Claim 24 (depends on 23)

The apparatus of claim 23, wherein the means for electrically coupling the first semiconductor device to at least the second semiconductor device comprises a printed circuit board (PCB).