# US 2014/0197518 A1 · Stacked structure semiconductor device

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- Number: US 2014/0197518 A1
- Document ID: US20140197518A1
- Status: Published application
- Kind: A1
- Application number: 14/154,246
- Filed: 2014-01-14
- Published: 2014-07-17
- Earliest claimed: 2013-01-17
- Assignees: STMicroelectronics S.r.l.
- Applicants: STMicroelectronics S.r.l.
- Inventors: Vittorio Giuseppe Maiorana; Alessandro Rizzo
- Web page: https://patentgrep.com/patent/US20140197518A1

## CPC

- H10D 1/47: Resistors having no potential barriers
- H10D 1/66: Conductor-insulator-semiconductor capacitors, e.g. MOS capacitors
- H10D 1/68: Capacitors having no potential barriers
- H10D 86/85: characterised by only passive components
- H10W 20/498: {Resistive arrangements or effects of, or between, wiring layers}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor device includes a capacitor formed in a semiconductor substrate of a first conductivity type. The capacitor includes: a heavily-doped layer of a second conductivity type placed over the substrate, a first insulating layer placed over the heavily-doped layer of the second conductivity type, and a first metal layer placed over the first insulating layer. The semiconductor device further includes comprises a second insulating layer deposited over the capacitor and at least one resistor formed over the second insulating layer. The resistor includes a layer of a resistive material region arranged between two regions of a second metal layer.

## Claims

### Claim 1

A semiconductor device, comprises:
a capacitor formed in a semiconductor substrate of a first conductivity type, said capacitor comprising:
a heavily-doped layer of a second conductivity type placed over said substrate,
a first insulating layer placed over said heavily-doped layer of the second conductivity type, and
a first metal layer placed over said first insulating layer,
a second insulating layer deposited over the capacitor, and
at least one resistor is formed over said second insulating layer using a layer comprising at least a resistive material region arranged between two regions of a second metal layer.

### Claim 2 (depends on 1)

The semiconductor device according to claim 1, wherein said heavily-doped layer is a well obtained in a lightly-doped epitaxial semiconductor layer of the second conductivity type grown on the semiconductor substrate of the first conductivity type .

### Claim 3 (depends on 1)

The semiconductor device according to claim 1, wherein said first insulating layer is a thermal Silicon dioxide layer.

### Claim 4 (depends on 1)

The semiconductor device according to claim 1, wherein said resistive layer is a Thin Film Resistor (TFR) layer.

### Claim 5

An integrated device, comprising:
a circuit including a resistor and a capacitor;
wherein the resistor is stacked on top of the capacitor.

### Claim 6 (depends on 5)

The integrated device of claim 5, wherein the capacitor is formed in a semiconductor substrate of a first conductivity type and comprises:
a heavily-doped layer of a second conductivity type placed over said substrate,
a first insulating layer placed over said heavily-doped layer of the second conductivity type, and
a first metal layer placed over said first insulating layer.

### Claim 7 (depends on 5)

The integrated device of claim 5, wherein the resistor is formed over a semiconductor substrate and comprises an insulating layer deposited over the substrate, and a resistive material region arranged between two regions of a metal layer.

### Claim 8 (depends on 5)

The integrated device of claim 5, wherein the capacitor includes a flat metal electrode formed over a semiconductor substrate and wherein the resistor includes a resistive material region formed over an insulating layer which is deposited on top of the flat metal electrode of the capacitor.

### Claim 9 (depends on 8)

The integrated device of claim 8, wherein the capacitor further includes an additional electrode formed of a buried doped semiconductor material formed in said substrate.

### Claim 10

A method, comprising:
manufacturing a capacitor over a semiconductor substrate of a first conductivity type, said capacitor being manufactured by:
forming a heavily-doped layer of a second conductivity type over said semiconductor substrate of a first conductivity type,
forming a first insulating layer over the heavily-doped layer of the second conductivity type, and
forming a first metal layer over the first insulating layer;
depositing a second insulting layer over the capacitor; and
forming at least one resistor by:
depositing a second metal layer over said insulating layer,
selectively removing the second metal layer for forming at least two regions of the second metal layer which are separated by a region without metal material, and
depositing a resistive material layer for forming at least one region of resistive material over said second insulating layer an between said two regions of the second metal layer.

### Claim 11 (depends on 10)

The method according to claim 10, further including, before forming the capacitor, growing a lightly-doped epitaxial semiconductor layer of the second conductivity type on the semiconductor substrate of the first conductivity type, and forming said heavily-doped layer as a well formed in said lightly-doped epitaxial semiconductor layer of the second conductivity type.

### Claim 12 (depends on 10)

The method according to claim 10, wherein said first insulating layer is a thermal Silicon dioxide layer.

### Claim 13 (depends on 10)

The method according to claim 10, wherein said resistive layer is a Thin Film Resistor (TFR) layer.