# US 2014/0197517 A1 · Trimming circuit for an integrated circuit and related integrated device > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2014/0197517 A1 - Document ID: US20140197517A1 - Status: Published application - Kind: A1 - Application number: 14/153,616 - Filed: 2014-01-13 - Published: 2014-07-17 - Earliest claimed: 2013-01-17 - Assignees: STMicroelectronics S.r.l. - Applicants: Stmicroelectronics S.R.L. - Inventors: Giuseppe Scilla - Web page: https://patentgrep.com/patent/US20140197517A1 ## CPC - H10D 84/613: {Combinations of vertical BJTs and one or more of diodes, resistors or capacitors} - H10D 84/0121: {the complementary BJTs being vertical BJTs} - H10D 84/038: {using silicon technology, e.g. SiGe} - H10D 84/209: {of only resistors} - H10W 20/493: {Fuses, i.e. interconnections changeable from conductive to non-conductive} - H01C 17/22: adapted for trimming - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 - H01C: RESISTORS ## Abstract A trimming circuit is configured to carry out a trimming operation on a device portion of an integrated circuit device. The trimming circuit includes: shunt fuses wherein each shunt fuse is coupled in parallel to a trimming resistance, further resistances wherein each further resistance is coupled in parallel to a respective shunt fuse. The circuit is configured to allow the flow of the trimming current when the respective shunt fuse is burnt during the trimming operation. ## Claims ### Claim 1 A trimming circuit configured to carry out a trimming operation on a device portion of an integrated circuit device, comprising: a plurality of shunt fuses, each shunt fuse of the plurality of shunt fuses being coupled in parallel to a trimming resistance of a plurality of trimming resistances, and a plurality of further resistances, each further resistance of the plurality of the further resistances being coupled in parallel to a respective shunt fuse of the plurality of shunt fuses and configured to allow the flow of the trimming current when the respective shunt fuse is burnt during the trimming operation. ### Claim 2 (depends on 1) The trimming circuit according to claim 1, wherein the trimming circuit is coupled to a first pin and a second pin of the integrated circuit device, said first pin being brought at a potential higher than the second pin during the trimming operation. ### Claim 3 (depends on 2) The trimming circuit according to claim 2, wherein the first pin is the ground pin of the integrated circuit device and the second pin is a dedicated pin. ### Claim 4 (depends on 2) The trimming circuit according to claim 2, wherein the trimming circuit is connected to the first pin and the second pin of the integrated circuit device by two respective switches, said switches being normally in off state and being configured to be on during the trimming operation. ### Claim 5 (depends on 4) The trimming circuit according to claim 4, wherein the switches configured to connect the trimming circuit with the first pin and the second pin of the integrated circuit device are respectively an npn bipolar transistor and a pnp bipolar transistor ### Claim 6 (depends on 1) The trimming circuit of claim 1, wherein said trimming circuit is a circuit part of an integrated circuit device. ### Claim 7 A semiconductor device, comprising: a trimming circuit formed in a semiconductor substrate of a first conductivity type, said trimming circuit comprising: a plurality of shunt fuses, each shunt fuse of the plurality of shunt fuses being coupled in parallel to a trimming resistance of a plurality of trimming resistances, and a plurality of further resistances, each further resistance of the plurality of the further resistances being coupled in parallel to a respective shunt fuse of the plurality of shunt fuses and configured to allow the flow of the trimming current when the respective shunt fuse is burnt during the trimming operation; wherein said pluralities of shunt fuses and further resistances are formed of: a highly-doped layer of a second conductivity type placed over said substrate, a first insulating layer placed selectively over said highly-doped layer of the second conductivity type to form a plurality of regions of insulating layer and a plurality of contact zones wherein no insulating layer is present so that each region of insulating layer is comprised between two adjacent contact zones, and a metal layer placed over said first insulating layer and in the contact zones to contact the highly-doped layer of a second conductivity type so that each further resistance of the plurality of further resistances is formed of each portion of said highly-doped layer of a second conductivity type comprises between two adjacent contact zones and under the region of the insulating layer comprised between said two adjacent contact zones and the respective shunt fuse of the plurality of shunt fuses is formed of the portion of said metal layer placed over said region of the insulating layer comprised between said two adjacent contact zones. ### Claim 8 (depends on 7) The semiconductor device according to claim 7, wherein an epitaxial layer of the second conductivity type is grown on the substrate, a well of the first conductivity type is formed in the epitaxial layer and the highly-doped layer of the second conductivity type is formed in the well of the first conductivity type. ### Claim 9 (depends on 7) The semiconductor device according to claim 7, wherein said semiconductor device comprises a plurality of metal paths departing from said plurality of contact zones toward a respective further plurality of contact zones of the respective plurality of trimming resistances. ### Claim 10 (depends on 7) The semiconductor device according to claim 7, wherein the trimming circuit is coupled to a first pad and a second pad respectively connected to a first pin and a second pin of the integrated circuit device, said first pin being brought at a potential higher than the second pin during the trimming operation. ### Claim 11 A method for manufacturing a semiconductor, comprising: forming a highly-doped layer of a second conductivity type over a semiconductor substrate of a first conductivity type, forming an insulating layer over the highly-doped layer of the second conductivity type, selectively removing the insulating layer to form a plurality of insulating layer regions and a plurality of contact zones wherein no insulating layer is present so that each region of insulating layer is comprised between two adjacent contact zones, forming a first metal layer over the insulating layer and in the contact zones to contact the highly-doped layer of a second conductivity type so as to form: a resistance comprising a portion of said highly-doped layer of a second conductivity type between two adjacent contact zones and under the region of the insulating layer comprised between said two adjacent contact zones and a shunt fuse formed of the portion of said metal layer placed over said region of the insulating layer between said two adjacent contact zones. ### Claim 12 (depends on 11) The method according to claim 11, wherein before the formation of the highly-doped layer of a second conductivity type the method comprises: growing an epitaxial layer of the second conductivity type on the substrate, forming a well of the first conductivity type in the epitaxial layer so that the highly-doped layer of the second conductivity type is formed in the well of the first conductivity type.