# US 2014/0197516 A1 · Integration of 3d stacked ic device with peripheral circuits

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- Number: US 2014/0197516 A1
- Document ID: US20140197516A1
- Status: Published application
- Kind: A1
- Application number: 13/739,914
- Filed: 2013-01-11
- Published: 2014-07-17
- Earliest claimed: 2013-01-11
- Assignees: Macronix International Co., Ltd.
- Inventors: Hang-Ting Lue; Yi-Hsuan Hsiao; Shih-Hung Chen; Yen-Hao Shih
- Web page: https://patentgrep.com/patent/US20140197516A1

## CPC

- H10P 74/203: {Structural properties, e.g. testing or measuring thicknesses, line widths, warpage, bond strengths or physical defects}
- H10B 43/27: the channels comprising vertical portions, e.g. U-shaped channels
- H10B 43/40: characterised by the peripheral circuit region
- H10D 62/115: {Dielectric isolations, e.g. air gaps}
- H10P 74/23: {characterised by multiple measurements, corrections, marking or sorting processes}
- H10B 41/27: the channels comprising vertical portions, e.g. U-shaped channels
- H10B 41/42: Simultaneous manufacture of periphery and memory cells
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10B: ELECTRONIC MEMORY DEVICES
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

An integrated circuit device includes a substrate including a first region and a second region. A pit is formed in the first region. A stack of active layers alternating with insulating layers is deposited in the pit. The stack includes a particular insulating layer. The particular insulating layer has a first thickness, where a sum of the first thickness, thickness of active layers, and thicknesses of other insulating layers is essentially equal to a depth of the pit. The first thickness is different than the thicknesses of the other insulating layers by an amount within a range of process variations for the depth of the pit, for the thicknesses of the active layers, and for the thicknesses of other insulating layers. The device includes a planarized surface over the first and second regions, where an uppermost one of the active layers has a top surface below the planarized surface.

## Claims

### Claim 1

A method for manufacturing an integrated circuit device, comprising:
etching a substrate to form a pit, the pit having a target depth below a top surface of the substrate;
measuring a depth of the etched pit;
depositing a stack of active layers alternating with insulating layers on the substrate at least in the etched pit, wherein the stack has at least one insulating layer having a thickness based on a difference between the target depth and the measured depth of the etched pit; and
applying a planarizing process to provide a planarized surface, wherein an uppermost one of the active layers has a top surface below the planarized surface.

### Claim 2 (depends on 1)

The method of claim 1, further comprising etching the stack in a pattern to define an isolation region in the pit separating the stack from a peripheral region.

### Claim 3 (depends on 2)

The method of claim 2, wherein the applying a planarizing process comprises:
forming a stopping layer over the stack, the isolation region, and the peripheral region;
depositing an insulation fill over the stopping layer in the isolation region;
polishing the insulation fill down to a level on or within the stopping layer; and
removing portions of the stopping layer above a level at the top surface of the substrate.

### Claim 4 (depends on 2)

The method of claim 2, further comprising forming components of peripheral circuits over the peripheral region.

### Claim 5 (depends on 1)

The method of claim 1, wherein the at least one insulating layer includes a bottom insulating layer in the stack, the bottom insulating layer having a target thickness based on the difference.

### Claim 6 (depends on 1)

The method of claim 1, wherein the at least one insulating layer includes a bottom insulating layer having a target thickness based on the difference, further comprising:
measuring a thickness of the deposited bottom insulating layer; and
depositing a second insulating layer over and in contact with the bottom insulating layer, wherein the second insulating layer has a second thickness based on the measured thickness of the deposited bottom insulating layer.

### Claim 7 (depends on 1)

The method of claim 1, wherein the target depth of the pit is greater than the thickness of the stack, further comprising:
measuring a thickness of the deposited stack; and
depositing a top insulating layer over the stack, wherein the top insulating layer has a thickness based on the measured thickness of the deposited stack and the measured depth of the pit.

### Claim 8 (depends on 1)

The method of claim 1, wherein the stack includes a lower sub-stack including some of the active layers alternating with insulating layers in the stack, and an upper sub-stack including others of the active layers alternating with insulating layers in the stack, and wherein the at least one insulating layer includes an intermediate insulating layer disposed in-between the lower sub-stack and the upper sub-stack, further comprising:
measuring a lower sub-stack thickness of the active layers and alternating insulating layers in the lower sub-stack, after deposition of the lower sub-stack and before deposition of the upper sub-stack; and
depositing the intermediate insulating layer over the lower sub-stack, wherein the intermediate insulating layer has a thickness based on the measured depth of the pit and the measured lower sub-stack thickness.

### Claim 9 (depends on 1)

The method of claim 1, further comprising:
forming interlayer connectors connected to respective active layers in the stack, the interlayer connectors extending from the respective active layers in the stack in the pit to a connector surface higher than the planarized surface; and
forming patterned conductor lines on top of the connector surface and connected to the respective interlayer connectors.

### Claim 10 (depends on 1)

The method of claim 1, further comprising:
etching the stack to define a plurality of active strips including at least a plurality of planes of active strips;
forming a memory layer over and in contact with side surfaces of active strips in the plurality of planes;
forming a layer of a second conductive material over and having a surface conformal with the memory layer;
etching the layer of the second conductive material to define a plurality of structures arranged orthogonally over, and having surfaces conformal with, the plurality of active strips in the plurality of planes; and
etching the memory layer to define memory elements in interface regions at cross-points between side surfaces of active strips in the plurality of planes and the plurality of structures.

### Claim 11

An integrated circuit device, comprising:
a substrate including a first region and a second region;
a pit formed in the first region, the pit having a depth;
a stack of active layers alternating with insulating layers deposited in the pit, wherein the stack includes:
a particular insulating layer having a first thickness, wherein a sum of the first thickness of the particular insulating layer, thicknesses of active layers, and thicknesses of other insulating layers in the stack is essentially equal to the depth, the first thickness being different than the thicknesses of the other insulating layers in the stack by an amount within a range of process variations for the depth of the pit, for the thicknesses of active layers, and for the thicknesses of other insulating layers; and
a planarized surface over the first region and the second region, wherein an uppermost one of the active layers has a top surface below the planarized surface.

### Claim 12 (depends on 11)

The integrated circuit device of claim 11, further comprising:
an isolation region in the pit separating the stack from the second region including a peripheral region; and
a stopping layer between the stack and the isolation region and between the isolation region and the peripheral region.

### Claim 13 (depends on 12)

The integrated circuit device of claim 12, further comprising components of peripheral circuits over the peripheral region.

### Claim 14 (depends on 11)

The integrated circuit device of claim 11, wherein the particular insulating layer includes a bottom insulating layer formed on a bottom of the pit.

### Claim 15 (depends on 11)

The integrated circuit device of claim 11, wherein the particular insulating layer is formed on a bottom insulating layer formed on a bottom of the pit, wherein a sum of the first thickness of the particular insulating layer, a second thickness of the bottom insulating layer, thicknesses of active layers, and thicknesses of other insulating layers in the stack is essentially equal to the target depth.

### Claim 16 (depends on 11)

The integrated circuit device of claim 11, wherein an uppermost one of the insulating layers is formed on the uppermost one of the active layers, and the particular insulating layer having the first thickness is formed on the uppermost one of the insulating layers.

### Claim 17 (depends on 11)

The integrated circuit device of claim 11, wherein the particular insulating layer includes an intermediate insulating layer formed between two adjacent active layers.

### Claim 18 (depends on 11)

The integrated circuit device of claim 11, further comprising:
interlayer connectors connected to respective active layers in the stack, the interlayer connectors extending from the respective active layers in the stack in the pit to a connector surface higher than the planarized surface; and
patterned conductor lines on top of the connector surface and connected to the respective interlayer connectors.

### Claim 19 (depends on 11)

The integrated circuit device of claim 11, further comprising:
a plurality of active strips including at least a plurality of planes of active strips;
a plurality of structures arranged orthogonally over, and having surfaces conformal with, the plurality of active strips in the plurality of planes; and
memory elements in interface regions at cross-points between side surfaces of active strips in the plurality of planes and the plurality of structures.