# US 2014/0197498 A1 · Integrated circuits and methods for fabricating integrated circuits with improved silicide contacts

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- Number: US 2014/0197498 A1
- Document ID: US20140197498A1
- Status: Published application
- Kind: A1
- Application number: 13/740,974
- Filed: 2013-01-14
- Published: 2014-07-17
- Earliest claimed: 2013-01-14
- Assignees: Globalfoundries Inc.
- Applicants: Globalfoundries, Inc.
- Inventors: Jan Hoentschel; Stefan Flachowsky; Nicolas Sasiat; Ran Yan
- Web page: https://patentgrep.com/patent/US20140197498A1

## CPC

- H10D 30/0212: {using self-aligned silicidation}
- H10D 30/60: Insulated-gate field-effect transistors [IGFET] (H10D30/40 takes precedence)
- H10D 84/0137: {the gate conductors being silicided}
- H10D 84/0147: {Manufacturing their gate sidewall spacers}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 64/015: {removing at least parts of gate spacers, e.g. disposable spacers}
- H10D 64/021: {using multiple gate spacer layers, e.g. bilayered sidewall spacers}
- H10D 64/693: {the insulator comprising nitrogen, e.g. nitrides, oxynitrides or nitrogen-doped materials}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

Integrated circuits and methods for fabricating integrated circuits are provided herein. In an embodiment, a method for fabricating an integrated circuit includes forming over a semiconductor substrate a gate structure. The method further includes depositing a non-conformal spacer material around the gate structure. A protection mask is formed over the non-conformal spacer material. The method etches the non-conformal spacer material and protection mask to form a salicidation spacer. Further, a self-aligned silicide contact is formed adjacent the salicidation spacer.

## Claims

### Claim 1

A method for fabricating an integrated circuit comprising:
forming a gate structure overlying a semiconductor substrate;
depositing a non-conformal spacer material around the gate structure;
forming a protection mask over the non-conformal spacer material;
etching the non-conformal spacer material and protection mask to form a salicidation spacer; and
forming a self-aligned silicide contact adjacent the salicidation spacer.

### Claim 2 (depends on 1)

The method of claim 1 wherein forming over a semiconductor substrate a gate structure comprises forming over the semiconductor substrate a gate electrode encapsulated by a gate cap and an electrode adjacent spacer, and wherein depositing a non-conformal spacer material around the gate structure comprises depositing a non-conformal spacer material around the electrode adjacent spacer.

### Claim 3 (depends on 2)

The method of claim 2 further comprising performing an ion implantation into the semiconductor substrate using the electrode adjacent spacer and gate cap as a mask.

### Claim 4 (depends on 2)

The method of claim 2 wherein forming over the semiconductor substrate a gate electrode encapsulated by a gate cap comprises forming a high-k dielectric layer on the semiconductor substrate and forming a metal electrode on the high-k dielectric layer.

### Claim 5 (depends on 1)

The method of claim 1 further comprising:
forming a conformal spacer around the gate structure;
performing an ion implantation into the semiconductor substrate using the conformal spacer as a mask; and
removing the conformal spacer before depositing the non-conformal spacer material around the gate structure.

### Claim 6 (depends on 5)

The method of claim 5 further comprising annealing the semiconductor substrate after performing the ion implantation and before forming a self-aligned silicide contact adjacent the salicidation spacer.

### Claim 7 (depends on 1)

The method of claim 1 wherein depositing a non-conformal spacer material around the gate structure comprises depositing silicon nitride by plasma-enhanced chemical vapor deposition (PECVD) around the gate structure.

### Claim 8 (depends on 7)

The method of claim 7 wherein forming a protection mask over the non-conformal spacer material comprises:
spin coating a protection layer onto the non-conformal spacer material; and
developing the protection layer to form the protection mask.

### Claim 9 (depends on 1)

The method of claim 1 wherein forming a self-aligned silicide contact adjacent the salicidation spacer comprises:
depositing a metal over the integrated circuit; and
reacting the metal with the semiconductor substrate to form the self-aligned silicide contact adjacent the salicidation spacer.

### Claim 10 (depends on 1)

The method of claim 1 wherein forming over a semiconductor substrate a gate structure comprises:
forming a high-k dielectric layer on the semiconductor substrate;
forming a metal electrode on the high-k dielectric layer;
forming a gate cap over the metal electrode; and
forming an electrode adjacent spacer around the metal electrode and gate cap;
wherein the method further comprises:
performing an ion implantation into the semiconductor substrate using the electrode adjacent spacer and gate cap as a mask.
forming a conformal spacer around the gate structure;
performing an ion implantation into the semiconductor substrate using the conformal spacer as a mask; and
removing the conformal spacer before depositing the non-conformal spacer material around the gate structure, wherein depositing the non-conformal spacer material around the gate structure comprises depositing a non-conformal spacer material around the electrode adjacent spacer.

### Claim 11

A method for fabricating an integrated circuit comprising:
forming over a semiconductor substrate a gate structure;
forming a conformal spacer around the gate structure;
performing an ion implantation into the semiconductor substrate using the conformal spacer as a mask; and
removing the conformal spacer;
depositing a non-conformal spacer material around the gate structure;
etching the non-conformal spacer material to form a salicidation spacer; and
forming a self-aligned silicide contact adjacent the salicidation spacer.

### Claim 12 (depends on 11)

The method of claim 11 wherein forming over a semiconductor substrate a gate structure comprises forming over the semiconductor substrate a gate electrode encapsulated by a gate cap and an electrode adjacent spacer, wherein forming a conformal spacer around the gate structure comprises forming a conformal spacer around the electrode adjacent spacer, and wherein depositing a non-conformal spacer material around the gate structure comprises depositing a non-conformal spacer material around the electrode adjacent spacer.

### Claim 13 (depends on 12)

The method of claim 12 wherein forming over the semiconductor substrate a gate electrode encapsulated by a gate cap comprises forming a high-k dielectric layer on the semiconductor substrate and forming a metal electrode on the high-k dielectric layer.

### Claim 14 (depends on 12)

The method of claim 12 further comprising:
performing an ion implantation into the semiconductor substrate using the electrode adjacent spacer and gate cap as a mask; and
performing an ion implantation into the semiconductor substrate using the conformal spacer as a mask.

### Claim 15 (depends on 11)

The method of claim 11 wherein depositing a non-conformal spacer material around the gate structure comprises depositing silicon nitride by plasma-enhanced chemical vapor deposition (PECVD) around the gate structure.

### Claim 16 (depends on 11)

The method of claim 11 wherein forming a self-aligned silicide contact adjacent the salicidation spacer comprises:
depositing a metal over the integrated circuit; and
reacting the metal with the semiconductor substrate to form the self-aligned silicide contact adjacent the salicidation spacer.

### Claim 17 (depends on 11)

The method of claim 11 further comprising forming a protection mask over the non-conformal spacer material.

### Claim 18 (depends on 17)

The method of claim 17 wherein etching the non-conformal spacer material to form a salicidation spacer comprises etching the non-conformal spacer material and the protection mask to form a salicidation spacer.

### Claim 19 (depends on 17)

The method of claim 17 wherein forming a protection mask over the non-conformal spacer material comprises:
spin coating a protection layer onto the non-conformal spacer material; and
developing the protection layer to form the protection mask.

### Claim 20

An integrated circuit comprising:
a gate structure formed on a semiconductor substrate and including a high-k dielectric layer, a metal electrode formed over the high-k dielectric layer, a gate cap formed over the metal electrode, and an electrode adjacent spacer formed around the gate cap and metal electrode;
a salicidation spacer formed around the gate structure;
a source/drain extension region formed in the semiconductor substrate and aligned with the electrode adjacent spacer;
a self-aligned silicide contact formed in the semiconductor substrate adjacent the salicidation spacer; and
a deep source/drain region formed in the semiconductor substrate in non-alignment with the silicidation spacer.