# US 2014/0197497 A1 · Native pmos device with low threshold voltage and high drive current and method of fabricating the same

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- Number: US 2014/0197497 A1
- Document ID: US20140197497A1
- Status: Published application
- Kind: A1
- Application number: 13/741,157
- Filed: 2013-01-14
- Published: 2014-07-17
- Earliest claimed: 2013-01-14
- Assignees: Broadcom Corporation
- Applicants: Broadcom Corporation
- Inventors: Akira ITO
- Web page: https://patentgrep.com/patent/US20140197497A1

## CPC

- H10D 62/371: {Inactive supplementary semiconductor regions, e.g. for preventing punch-through, improving capacity effect or leakage current}
- H10D 30/0227: {having both lightly-doped source and drain extensions and source and drain regions self-aligned to the sides of the gate, e.g. lightly-doped drain [LDD] MOSFET or double-diffused drain [DDD] MOSFET}
- H10D 30/601: {having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs (lightly doped source or drain extensions for TFTs H10D30/6715)}
- H10D 30/797: {being in source or drain regions, e.g. SiGe source or drain}
- H10D 62/116: {adjoining the input or output regions of field-effect devices, e.g. adjoining source or drain regions}
- H10D 62/126: {Top-view geometrical layouts of the regions or the junctions}
- H10D 62/151: {of IGFETs (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713)}
- H10D 62/822: comprising only Group IV materials heterojunctions, e.g. Si/Ge heterojunctions
- H10D 64/01326: {Aspects related to lithography, isolation or planarisation of the conductor}
- H10D 64/665: {the conductor comprising a layer of elemental metal contacting the insulator, e.g. tungsten or molybdenum (having lateral variation H10D64/671)}
- H10D 64/691: {comprising metallic compounds, e.g. metal oxides or metal silicates (insulators comprising nitrogen H10D64/693)}
- H10D 84/0142: {the gate conductors having different shapes or dimensions}
- H10D 84/0167: {Manufacturing their channels}
- H10D 84/017: {Manufacturing their source or drain regions, e.g. silicided source or drain regions}
- H10D 84/0191: {Manufacturing their doped wells}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 30/0275: {forming single crystalline semiconductor source or drain regions resulting in recessed gates, e.g. forming raised source or drain regions}
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D 64/666: {the conductor further comprising additional layers}
- H10W 10/014: {using trench refilling with dielectric materials, e.g. shallow trench isolations}
- H10W 10/17: formed using trench refilling with dielectric materials, e.g. shallow trench isolations
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A native p-type metal oxide semiconductor (PMOS) device that exhibits a low threshold voltage and a high drive current over a varying range of short channel lengths and a method for fabricating the same is discussed in the present disclosure. The source and drain regions of the native PMOS device, each include a strained region, a heavily doped raised region, and a lightly doped region. The gate region includes a stacked layer of a gate oxide having a high-k dielectric material, a metal, and a contact metal. The high drive current of the native PMOS device is primarily influenced by the increased carrier mobility due to the strained regions, the lower drain resistance due to the raised regions, and the higher gate capacitance due to the high-k gate oxide of the native PMOS device.

## Claims

### Claim 1

A P-type metal-oxide semiconductor (PMOS) device, comprising:
a substrate having a first material;
a source region having a second material configured to provide a first strained region;
a drain region having the second material configured to provide a second strained region; and
a gate region between the source region and the drain region, the gate region comprising:
a first layer having a first thickness;
a second layer having a second thickness, the second thickness being greater than the first thickness; and
a third layer having a third thickness, the third thickness being greater than the second thickness.

### Claim 2 (depends on 1)

The PMOS device of claim 1, wherein the source region further comprises:
a first lightly doped region having a first doping concentration of carriers, and
a first heavily doped region having a second doping concentration of the carriers; and
wherein the drain region further comprises:
a second lightly doped region having the first doping concentration of the carriers, and
a second heavily doped region having the second doping concentration of the carriers, wherein the first doping concentration is smaller than the second doping concentration.

### Claim 3 (depends on 2)

The PMOS device of claim 2, wherein:
a first portion of the first lightly doped region is positioned in the first strained region;
a second portion of the first lightly doped region extends out from the first strained region, such that the extended portion is substantially in contact with the gate region;
a first portion of the second lightly doped region is positioned in the second strained region; and
a second portion of the second lightly doped region extends out from the second strained region, such that the extended portion is substantially in contact with the gate region.

### Claim 4 (depends on 2)

The PMOS device of claim 2, wherein the first heavily doped region is configured to be in the first strained region, and between the first lightly doped region and a shallow trench isolation (STI) region; and
wherein the second heavily doped region is configured to be in the second strained region and between the second lightly doped region and the STI region.

### Claim 5 (depends on 1)

The PMOS device of claim 1, wherein vertical dimensions of the first and second strained regions are greater than or equal to vertical dimensions of the first and second heavily doped regions.

### Claim 6 (depends on 1)

The PMOS device of claim 1, wherein a first side of the first strained region is substantially aligned vertically with a first side of the gate region,
wherein a second side of the first strained region is substantially in contact with at least a first portion of an inner perimeter side of a shallow trench isolation (STI) region,
wherein a first side of the second strained region is substantially aligned vertically with a second side of the gate region, and
wherein a second side of the second strained region is substantially in contact with at least a second portion of the inner perimeter side of the STI region.

### Claim 7 (depends on 1)

The PMOS device of claim 1, wherein the second material comprises a compound semiconductor material.

### Claim 8 (depends on 7)

The PMOS device of claim 7, wherein the compound semiconductor material comprises a silicon germanium material.

### Claim 9 (depends on 1)

The PMOS device of claim 1, wherein the first, second, and third layers form stacked layers, and
wherein the first, second, and third layers are configured to have approximately equal lateral dimensions.

### Claim 10 (depends on 1)

The PMOS device of claim 1, wherein the first layer is configured to be a high-k gate region oxide layer having a high-k dielectric material selected from the group consisting of: hafnium dioxide and zirconium dioxide,
wherein the second layer is configured to be a metal layer having a metal selected from the group consisting of: tungsten and titanium, and
wherein the third layer is configured to be a contact metal layer having a contact metal selected from the group consisting of: aluminum and copper.

### Claim 11 (depends on 1)

The PMOS device of claim 1, further comprising:
a first halo implant region in substantial contact with the first strained region; and
a second halo implant region in substantial contact with the second strained region.

### Claim 12 (depends on 1)

The PMOS device of claim 1, wherein the semiconductor device is characterized as having a threshold voltage of approximately zero volts.

### Claim 13

A P-type metal oxide semiconductor (PMOS) device, comprising:
a substrate having a first material,
a source region having a first raised region, a top side of the first raised region being raised above a top side of the substrate,
a drain region having a second raised region, a top side of the second raised region being raised above the top side of the substrate,
a gate region between the source region and drain region, the gate region comprising:
a first layer having a first thickness;
a second layer having a second thickness, the second thickness being greater than the first thickness; and
a third layer having a third thickness, the third thickness being greater than the second thickness.

### Claim 14 (depends on 13)

The PMOS device of claim 13, wherein the source region further comprises:
a first strained region having a second material, and
a first lightly doped region positioned in the first strained region, the first lightly doped region having a portion extending laterally out from the first strained region, such that the extended portion is substantially in contact with the gate region; and
wherein the drain region further comprises:
a second strained region having the second material,
a second lightly doped region positioned in the second strained region, the second lightly doped region having a portion extending laterally out from the second strained region, such that the extended portion is substantially in contact with the gate region.

### Claim 15 (depends on 13)

The PMOS device of claim 13, wherein the first raised region comprises:
a first portion configured to be in the first strained region and between the first lightly doped region and a shallow trench isolation (STI) region, and
a second portion configured to extend vertically out of the first strained region; and
wherein the second raised region comprises:
a first portion configured to be in the second strained region and between the second lightly doped region and the STI region, and
a second portion configured to extend vertically out of the second strained region.

### Claim 16 (depends on 13)

The PMOS device of claim 13, wherein vertical dimensions of the vertically extended second portions of the respective first and second raised regions are approximately half of a vertical dimension of the gate region.

### Claim 17 (depends on 14)

The PMOS device of claim 14, wherein a first side of the first strained region is substantially aligned vertically with a first side of the gate region;
wherein a second side of the first strained region is substantially in contact with at least a first portion of an inner perimeter side of a shallow trench isolation (STI) region;
wherein a first side of the second strained region is substantially aligned vertically with a second side of the gate region; and
wherein a second side of the second strained region is substantially in contact with at least a second portion of the inner perimeter side of the STI region.

### Claim 18 (depends on 14)

The PMOS device of claim 14, wherein the second material comprises a compound semiconductor material.

### Claim 19 (depends on 14)

The PMOS device of claim 14, wherein the compound semiconductor material comprises a silicon germanium material.

### Claim 20 (depends on 1)

The PMOS device of claim 1, wherein: the first, second, and third layers form stacked layers, and
wherein the first, second, and third layers are configured to have approximately equal lateral dimensions.

### Claim 21 (depends on 20)

The PMOS device of claim 20, wherein the first layer is configured to be a high-k gate region oxide layer having a high-k dielectric material selected from the group consisting of: hafnium dioxide and zirconium dioxide,
wherein the second layer is configured to be a metal layer having a metal selected from the group consisting of: tungsten and titanium, and
wherein the third layer is configured to be a contact metal layer having a contact metal selected from the group consisting of: aluminum and copper.

### Claim 22 (depends on 1)

The PMOS device of claim 1, wherein the semiconductor device is characterized as having a threshold voltage of approximately zero volts.

### Claim 23

A semiconductor device, comprising:
a source region having:
a first raised region, and
a first strained region;
a drain region having:
a second raised region, and
a second strained region; and
a gate region having stacked metal layers.