# US 2014/0197496 A1 · Semiconductor Structure with Suppressed STI Dishing Effect at Resistor Region

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- Number: US 2014/0197496 A1
- Document ID: US20140197496A1
- Status: Published application
- Kind: A1
- Application number: 14/221,466
- Filed: 2014-03-21
- Published: 2014-07-17
- Earliest claimed: 2011-05-25
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Company, Ltd.
- Inventors: Harry-Hak-Lay Chuang; Ming Zhu; Lee-Wee Teo; Bao-Ru Young
- Web page: https://patentgrep.com/patent/US20140197496A1

## CPC

- H10D 84/811: {Combinations of field-effect devices and one or more diodes, capacitors or resistors}
- H10D 62/115: {Dielectric isolations, e.g. air gaps}
- H10D 84/817: {Combinations of field-effect devices and resistors only}
- H10P 50/283: {by chemical means}
- H10P 95/064: {the removal being chemical etching}
- H10W 10/014: {using trench refilling with dielectric materials, e.g. shallow trench isolations}
- H10W 10/17: formed using trench refilling with dielectric materials, e.g. shallow trench isolations
- H10D 1/47: Resistors having no potential barriers
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

An integrated circuit includes a semiconductor substrate; a first shallow trench isolation (STI) feature of a first width and a second STI feature of a second width in a semiconductor substrate. The first width is less than the second width. The first STI feature has an etch-resistance less than that of the second STI feature.

## Claims

### Claim 1

An integrated circuit, comprising:
a semiconductor substrate; and
a first shallow trench isolation (STI) feature of a first width and a second STI feature of a second width in a semiconductor substrate, wherein the first width is less than the second width, and the first STI feature has an etch-resistance less than that of the second STI feature.

### Claim 2 (depends on 1)

The integrated circuit of claim 1, wherein the first STI feature includes an impurity of a first doping concentration substantially higher than a second doping concentration of the impurity in the second STI feature.

### Claim 3 (depends on 2)

The integrated circuit of claim 2, wherein the impurity includes an n-type dopant.

### Claim 4 (depends on 3)

The integrated circuit of claim 3, wherein the impurity includes one of phosphorous and arsenic.

### Claim 5 (depends on 1)

The integrated circuit of claim 1, further comprising:
a first field-effect transistor (FET) disposed in a first active region of the semiconductor substrate; and
a first resistor disposed on the second STI feature,
wherein the first FET include a first gate, and
the first resistor and the first gate include a polysilicon layer.

### Claim 6 (depends on 5)

The integrated circuit of claim 5, further comprising a second FET disposed in a second active region of the semiconductor substrate, wherein
the first FET includes a first gate oxide layer of a first thickness; and
the second FET includes a second gate oxide layer of a second thickness less than the first thickness.

### Claim 7 (depends on 5)

The integrated circuit of claim 5, further comprising a second resistor that is disposed on the second STI feature, wherein the first and second resistors are spaced away within the second width.

### Claim 8

An integrated circuit, comprising:
a semiconductor substrate;
a first shallow trench isolation (STI) feature of a first width and a second STI feature of a second width in a semiconductor substrate, the first width being substantially less than the second width;
a first field-effect transistor (FET) disposed in a first active region of the semiconductor substrate; and
a plurality of resistors disposed on the second STI feature and spaced away from each other within the second width,
wherein the first STI feature includes an impurity and has an etch-resistance less than that of the second STI feature.

### Claim 9 (depends on 8)

The integrated circuit of claim 8, wherein the impurity includes an n-type dopant.

### Claim 10 (depends on 9)

The integrated circuit of claim 9, wherein the impurity includes one of phosphorous and arsenic.

### Claim 11 (depends on 8)

The integrated circuit of claim 8, wherein the first FET includes a first gate stack disposed in the first active region.

### Claim 12 (depends on 11)

The integrated circuit of claim 11, wherein the first gate stack and the plurality of resistors include a polysilicon layer.

### Claim 13 (depends on 11)

The integrated circuit of claim 11, further comprising a second FET disposed in a second active region, wherein the second FET includes a second gate stack.

### Claim 14 (depends on 13)

The integrated circuit of claim 13, wherein
the first FET includes a first gate oxide layer of a first thickness; and
the second FET includes a second gate oxide layer of a second thickness less than the first thickness.

### Claim 15 (depends on 14)

The integrated circuit of claim 14, wherein the first STI feature and second STI feature include silicon oxide.

### Claim 16

An integrated circuit, comprising:
a semiconductor substrate;
a first shallow trench isolation (STI) feature of a first width and a second STI feature of a second width in a semiconductor substrate, the first width being substantially less than the second width;
a first resistor disposed on the second STI feature;
a first field-effect transistor (FET) for an input/output (I/O) circuit disposed in a first active region of the semiconductor substrate, the first FET including a first gate oxide layer of a first thickness; and
a second FET disposed in a second active region of the semiconductor substrate, the second FET including a second gate oxide layer of a second thickness substantially less than the first thickness.

### Claim 17 (depends on 16)

The integrated circuit of claim 16, wherein the first STI feature has a first etch-resistivity less than that of the second STI feature.

### Claim 18 (depends on 16)

The integrated circuit of claim 16, wherein the impurity includes an n-type dopant selected from one of phosphorous and arsenic.

### Claim 19 (depends on 16)

The integrated circuit of claim 16, wherein
the first FET includes a first gate disposed on the first gate oxide layer;
the second FET includes a second gate disposed on the second gate oxide layer; and
the first gate, the second gate and the first resistor include polysilicon.

### Claim 20 (depends on 16)

The integrated circuit of claim 16, further comprising a second resistor that is disposed on the second STI feature and is spaced away from the first resistor.