# US 2014/0197495 A1 · Semiconductor device and method of forming the same

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- Number: US 2014/0197495 A1
- Document ID: US20140197495A1
- Status: Published application
- Kind: A1
- Application number: 14/218,398
- Filed: 2014-03-18
- Published: 2014-07-17
- Earliest claimed: 2007-04-27
- Assignees: Elpida Memory, Inc.
- Applicants: Elpida Memory, Inc.
- Inventors: Yoshikazu MORIWAKI
- Web page: https://patentgrep.com/patent/US20140197495A1

## CPC

- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/0177: {the gate conductors having different materials or different implants}
- H10D 84/0181: {Manufacturing their gate insulating layers}
- H10D 84/0186: {Manufacturing their interconnections or electrodes, e.g. source or drain electrodes}
- H10D 84/859: {comprising both N-type and P-type wells, e.g. twin-tub}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A semiconductor device may include an n-MOS transistor, and a p-MOS transistor. The p-MOS transistor may include, but is not limited to, a gate insulating film and a gate electrode. The gate electrode may have an adjacent portion that is adjacent to the gate insulating film. The adjacent portion may include a polysilicon that contains an n-type dopant and a p-type dopant.

## Claims

### Claim 1

A semiconductor device comprising:
an n-MOS transistor; and
a p-MOS transistor that comprises a gate insulating film and a gate electrode, the gate electrode having an adjacent portion that is adjacent to the gate insulating film, the adjacent portion comprising a polysilicon that contains an n-type dopant and a p-type dopant.

### Claim 2 (depends on 1)

The semiconductor device according to claim 1, wherein the adjacent portion has a thickness of at least 30 nanometers from the interface between the gate electrode and the gate insulating film.

### Claim 3 (depends on 1)

The semiconductor device according to claim 1, wherein the adjacent portion has a compositional ratio of the n-type dopant to the p-type dopant in the range of 10% to 40%.

### Claim 4 (depends on 1)

The semiconductor device according to claim 1, wherein the gate electrode has a stacked structure that comprises a lower portion that includes the adjacent portion, and an upper portion over the lower portion,
the lower portion comprises the polysilicon containing the n-type dopant and the p-type dopant, and
the upper portion contains the polysilicon containing the p-type dopant.

### Claim 5

A method of forming a semiconductor device comprising an n-MOS transistor and a p-MOS transistor, the method comprising:
forming a gate insulating film over an n-MOS transistor region and a p-MOS transistor region of a semiconductor substrate;
forming a first polysilicon layer over the gate insulating film, the first polysilicon layer containing an n-type dopant;
forming a second polysilicon layer over the first polysilicon layer, the second polysilicon layer being substantially free of any dopant;
patterning the stack of the first and second polysilicon layers to form gate electrode structures in the n-MOS transistor region and the p-MOS transistor region;
carrying out a first ion-implantation process of an n-type dopant to the n-MOS transistor region, thereby introducing the n-type dopant into the first and second polysilicon layers in the n-MOS transistor region and into source and drain formation regions of the semiconductor substrate in the n-MOS transistor region; and
carrying out a second ion-implantation process of a p-type dopant to the p-MOS transistor region, thereby introducing the p-type dopant into the first and second polysilicon layers in the p-MOS transistor region and into source and drain formation regions of the semiconductor substrate in the p-MOS transistor region.

### Claim 6 (depends on 5)

The method according to claim 5, further comprising:
forming side walls on side faces of the gate electrode structures in the n-MOS transistor region and the p-MOS transistor region, after carrying out the first and second ion-implantation processes;
carrying out a third ion-implantation process of an n-type dopant to the n-MOS transistor region using the side walls as a mask, thereby introducing the n-type dopant into the first and second polysilicon layers in the n-MOS transistor region and into the source and drain formation regions of the semiconductor substrate in the n-MOS transistor region; and
carrying out a fourth ion-implantation process of a p-type dopant to the p-MOS transistor region using the side walls as a mask, thereby introducing the p-type dopant into the first and second polysilicon layers in the p-MOS transistor region and into the source and drain formation regions of the semiconductor substrate in the p-MOS transistor region.

### Claim 7 (depends on 6)

The method according to claim 6, further comprising:
carrying out an annealing process for the semiconductor substrate, after carrying out the third and fourth ion-implantation processes.

### Claim 8 (depends on 5)

The method according to claim 5, wherein the first ion-implantation process is carried out at a dose in the range of 1E13 atoms/cm2 to 1E15 atoms/cm2.