# US 2014/0197494 A1 · Trench silicide and gate open with local interconnect with replacement gate process > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2014/0197494 A1 - Document ID: US20140197494A1 - Status: Published application - Kind: A1 - Application number: 14/217,905 - Filed: 2014-03-18 - Published: 2014-07-17 - Earliest claimed: 2011-11-14 - Assignees: Advanced Micro Devices, Inc. - Applicants: Advanced Micro Devices, Inc. - Inventors: Richard T. Schultz - Web page: https://patentgrep.com/patent/US20140197494A1 ## CPC - H10D 84/83: of only insulated-gate FETs [IGFET] - H10W 20/069: {by forming self-aligned vias or self-aligned contact plugs} - H10W 20/0698: {Local interconnections} - H10W 20/071: {of dielectric parts thereof} - H10W 20/075: {of multilayered thin functional dielectric layers} - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract A semiconductor device fabrication process includes forming insulating mandrels over replacement metal gates on a semiconductor substrate with first gates having sources and drains and at least one second gate being isolated from the first gates. Mandrel spacers are formed around each insulating mandrel. The mandrels and mandrel spacers include the first insulating material. A second insulating layer of the second insulating material is formed over the transistor. One or more first trenches are formed to the sources and drains of the first gates by removing the second insulating material between the insulating mandrels. A second trench is formed to the second gate by removing portions of the first and second insulating materials above the second gate. The first trenches and the second trench are filled with conductive material to form first contacts to the sources and drains of the first gates and a second contact to the second gate. ## Claims ### Claim 1 A semiconductor device, comprising: a plurality of replacement metal gates on a semiconductor substrate, wherein first gates have sources and drains and at least one second gate is isolated from the first gates; gate spacers of a first insulating material around each first gate; a first insulating layer of a second insulating material between the gate spacers, wherein at least some of the second insulating material overlies sources and drains of the first gates; one or more insulating mandrels aligned over the gates, wherein the insulating mandrels comprise the first insulating material; mandrel spacers around each insulating mandrel, wherein the mandrel spacers comprise the first insulating material; one or more first contacts to the sources and drains of the first gates through the first insulating layer between the mandrel spacers; a second contact to the at least one second gate through the first insulating material above the second gate; a third insulating layer over the transistor; and one or more local interconnects that contact the first contacts and the second contact through the third insulating layer. ### Claim 2 (depends on 1) The device of claim 1, wherein the second contact to the at least one second gate is through the mandrel above the second gate. ### Claim 3 (depends on 1) The device of claim 1, wherein each insulating mandrel has approximately the same width as its underlying gate with each mandrel being at least as wide as its underlying gate. ### Claim 4 (depends on 1) The device of claim 1, wherein each mandrel spacer has a profile that slopes from being wider at the bottom to narrower at the top. ### Claim 5 (depends on 1) The device of claim 1, wherein the first contacts have a profile that matches the slope of the mandrel spacers such that the first contacts are wider at the top than at the bottom ### Claim 6 (depends on 1) The device of claim 1, wherein the first contacts are not shorted to the gates. ### Claim 7 (depends on 1) The device of claim 1, wherein the third insulating layer comprises the second insulating material. ### Claim 8 (depends on 1) The device of claim 1, wherein the first gates are located in an active region of the semiconductor device and the second gate is located in an isolation region of the semiconductor device. ### Claim 9 A computer readable storage medium storing a plurality of instructions which, when executed, generate a semiconductor device that comprises: a plurality of replacement metal gates on a semiconductor substrate, wherein first gates have sources and drains and at least one second gate is isolated from the first gates; gate spacers of a first insulating material around each first gate; a first insulating layer of a second insulating material between the gate spacers, wherein at least some of the second insulating material overlies sources and drains of the first gates; one or more insulating mandrels aligned over the gates, wherein the insulating mandrels comprise the first insulating material; mandrel spacers around each insulating mandrel, wherein the mandrel spacers comprise the first insulating material; one or more first contacts to the sources and drains of the first gates through the first insulating layer between the mandrel spacers; a second contact to the at least one second gate through the first insulating material above the second gate; a third insulating layer over the transistor; and one or more local interconnects that contact the first contacts and the second contact through the third insulating layer. ### Claim 10 (depends on 9) The computer readable storage medium of claim 9, wherein the second contact to the at least one second gate is through the mandrel above the second gate. ### Claim 11 (depends on 9) The computer readable storage medium of claim 9, wherein each insulating mandrel has approximately the same width as its underlying gate with each mandrel being at least as wide as its underlying gate. ### Claim 12 (depends on 9) The computer readable storage medium of claim 9, wherein each mandrel spacer has a profile that slopes from being wider at the bottom to narrower at the top. ### Claim 13 (depends on 9) The computer readable storage medium of claim 9, wherein the first contacts have a profile that matches the slope of the mandrel spacers such that the first contacts are wider at the top than at the bottom ### Claim 14 (depends on 9) The computer readable storage medium of claim 9, wherein the first contacts are not shorted to the gates. ### Claim 15 (depends on 9) The computer readable storage medium of claim 9, wherein the third insulating layer comprises the second insulating material. ### Claim 16 (depends on 9) The computer readable storage medium of claim 9, wherein the first gates are located in an active region of the semiconductor device and the second gate is located in an isolation region of the semiconductor device.