# US 2014/0197492 A1 · Semiconductor device and fabrication method

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- Number: US 2014/0197492 A1
- Document ID: US20140197492A1
- Status: Published application
- Kind: A1
- Application number: 14/069,693
- Filed: 2013-11-01
- Published: 2014-07-17
- Earliest claimed: 2013-01-11
- Assignees: Semiconductor Manufacturing International (Shanghai) Corporation
- Applicants: Semiconductor Manufacturing International (Shanghai) Corporation
- Inventors: QIUHUA HAN
- Web page: https://patentgrep.com/patent/US20140197492A1

## CPC

- H10D 30/791: {Arrangements for exerting mechanical stress on the crystal lattice of the channel regions}
- H10D 30/024: {of fin field-effect transistors [FinFET]}
- H10D 30/62: Fin field-effect transistors [FinFET]
- H10D 30/6215: {having multiple independently-addressable gate electrodes}
- H10D 30/751: {having composition variations in the channel regions}
- H10D 30/798: {being provided in or under the channel regions}
- H10D 62/822: comprising only Group IV materials heterojunctions, e.g. Si/Ge heterojunctions
- H10D 62/8325: {Silicon carbide}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

Semiconductor devices and fabrication methods are provided. In an exemplary method, a semiconductor layer including a first opening can be provided. The first opening can be filled with a stress material. The stress material can then be etched to form a second opening having a width less than a width of the first opening to leave a stress material layer in the semiconductor layer and on each sidewall of the second opening. The semiconductor layer can be etched to form a fin structure on a sidewall surface of the stress material layer. A main gate structure can be formed on the sidewall surface of the fin structure. A back gate structure can be formed on the sidewall surface of the stress material layer.

## Claims

### Claim 1

A method of fabricating an semiconductor device, comprising:
providing a semiconductor layer including a first opening therein;
filling the first opening with a stress material;
etching the stress material to form a second opening having a width less than a width of the first opening to leave a stress material layer in the semiconductor layer and on each sidewall of the second opening;
etching the semiconductor layer to form a fin structure on a sidewall surface of the stress material layer;
forming a main gate structure on the sidewall surface of the fin structure; and
forming a back gate structure on the sidewall surface of the stress material layer.

### Claim 2 (depends on 1)

The method of claim 1, wherein forming the stress material layer includes:
forming a first mask layer having a third opening on the semiconductor layer,
forming the first opening by etching the semiconductor layer using the first mask layer as an etch mask,
forming a sidewall spacer on each sidewall of the third opening in the first mask layer,
etching the stress material to form the second opening using the sidewall spacer and the first mask layer as an etch mask, and
forming the stress material layer in the semiconductor layer and on the each sidewall of the second opening.

### Claim 3 (depends on 2)

The method of claim 2, wherein forming the fin structure includes:
removing the sidewall spacer from each sidewall of the third opening in the first mask layer,
removing a portion of the first mask layer adjacent to the sidewall spacer of the third opening to form a fourth opening in a remaining first mask layer with a larger width than the third opening,
forming a second mask layer in the second opening and the fourth opening,
removing the remaining first mask layer,
etching the semiconductor layer using the second mask layer as mask to form the fin structure on each sidewall surface of the stress material layer, and
removing the second mask layer.

### Claim 4 (depends on 3)

The method of claim 3, wherein the second mask layer is formed of a material different from a material for the first mask layer.

### Claim 5 (depends on 3)

The method of claim 3, wherein removing the portion of the first mask layer adjacent to the sidewall spacer of the third opening includes a dry etching process or a wet etching process.

### Claim 6 (depends on 1)

The method of claim 1, wherein the depth of the second opening is greater than or equal to the depth of the first opening into the semiconductor layer.

### Claim 7 (depends on 1)

The method of claim 1, wherein the stress material layer is formed of silicon carbide when the semiconductor device is a PMOS transistor and the stress material layer is formed of germanium-silicon when the semiconductor device is an NMOS transistor.

### Claim 8 (depends on 1)

The method of claim 1, wherein forming the main gate structure and the back gate structure includes:
forming a gate dielectric layer on the sidewall surface and a top surface of each of the fin structure and the stress material layer,
forming a gate electrode on gate dielectric layer, and
removing the dielectric layer and the gate electrode on the top surface of each of the fin structure and the stress material layer by an etching back or a chemical mechanical polishing to form the main gate structure on the sidewall surface of the fin structure, and to form the back gate structure on the sidewall surface of the stress material layer.

### Claim 9 (depends on 1)

The method of claim 1, wherein the first opening has a width ranging from about 10 nm to about 100 nm and a depth ranging from about 10 nm to about 100 nm.

### Claim 10 (depends on 1)

The method of claim 1, further including forming a source region and a drain region in the fin structure at both sides of each of the main gate structure and the back gate structure.

### Claim 11 (depends on 1)

The method of claim 1, wherein the semiconductor layer includes a bulk silicon, a bulk germanium, a top silicon layer of a silicon-on-insulator substrate, or a top germanium layer of a germanium-on-insulator substrate.

### Claim 12 (depends on 1)

The method of claim 1, wherein, when the semiconductor layer is formed of a bulk silicon or a bulk germanium, the method further includes:
forming a dielectric layer on the semiconductor layer after formation of the fin structure.

### Claim 13 (depends on 1)

The method of claim 1, wherein when the semiconductor layer is formed of a top silicon layer of a silicon-on-insulator substrate, or a top germanium layer of a germanium-on-insulator substrate, the second opening has a depth equal to the thickness of the top silicon layer or the top germanium layer.

### Claim 14

A semiconductor device comprising:
a semiconductor layer;
a fin structure on the semiconductor layer;
a stress material layer having a first sidewall disposed on a first sidewall surface of the fin structure;
a main gate structure disposed on a second sidewall surface of the fin structure, wherein the first sidewall surface of the fin structure is opposite to the second sidewall surface of the fin structure; and
a back gate structure disposed on a second sidewall surface of the stress material layer, wherein the stress material layer is disposed between the fin structure and the back gate structure.

### Claim 15 (depends on 14)

The device of claim 14, wherein the stress material layer has a width ranging from about 5 nm to about 15 nm.

### Claim 16 (depends on 14)

The device of claim 14, wherein the fin structure has a width ranging from about 5 nm to about 30 nm.

### Claim 17 (depends on 14)

The device of claim 14, wherein the stress material layer is formed of silicon carbide when the semiconductor device is a PMOS transistor and the stress material layer is formed of germanium-silicon when the semiconductor device is an NMOS transistor.

### Claim 18 (depends on 14)

The device of claim 14, further including a source region and a drain region disposed in the fin structure at both sides of each of the main gate structure and the back gate structure.

### Claim 19 (depends on 14)

The device of claim 14, wherein the semiconductor layer includes a bulk silicon, a bulk germanium, a top silicon layer of a silicon-on-insulator substrate, or a top germanium layer of a germanium-on-insulator substrate.

### Claim 20 (depends on 14)

The device of claim 14, wherein the semiconductor layer is a bulk silicon or a bulk germanium, and wherein a dielectric layer is disposed between the semiconductor layer and each of the main gate structure and the back gate structure.