# US 2014/0197491 A1 · Semiconductor device and manufacturing method thereof

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- Number: US 2014/0197491 A1
- Document ID: US20140197491A1
- Status: Published application
- Kind: A1
- Application number: 14/156,549
- Filed: 2014-01-16
- Published: 2014-07-17
- Earliest claimed: 2013-01-17
- Assignees: Fuji Electric Co., Ltd.
- Applicants: Fuji Electric Co., Ltd.
- Inventors: Masaharu YAMAJI
- Web page: https://patentgrep.com/patent/US20140197491A1

## CPC

- H10D 62/114: {PN junction isolations}
- H10D 30/021: {of FETs having insulated gates [IGFET]}
- H10D 30/0221: {having asymmetry in the channel direction, e.g. lateral high-voltage MISFETs having drain offset region or extended-drain MOSFETs [EDMOS]}
- H10D 30/60: Insulated-gate field-effect transistors [IGFET] (H10D30/40 takes precedence)
- H10D 30/603: {having asymmetry in the channel direction, e.g. lateral high-voltage MISFETs having drain offset region or extended drain IGFETs [EDMOS]}
- H10D 62/106: {having supplementary regions doped oppositely to or in rectifying contact with regions of the semiconductor bodies, e.g. guard rings with PN or Schottky junctions}
- H10D 62/151: {of IGFETs (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713)}
- H10D 89/813: {specially adapted to provide an electrical current path other than the field-effect induced current path}
- H10P 30/22: using masks
- H10D 62/115: {Dielectric isolations, e.g. air gaps}
- H10W 10/031: {of isolation regions comprising PN junctions}
- H10W 10/30: Isolation regions comprising PN junctions
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor device and manufacturing method are disclosed which provide increased ESD resistance. By disposing a slit mask when forming a second p-type well layer, impurity concentration of the second p-type well layer is partially reduced. By forming a second n-type offset layer in the second p-type well layer having decreased impurity concentration, it is possible to increase thickness of the second n-type offset layer in this place compared with that heretofore known. By increasing thickness of the second n-type offset layer, a depletion layer does not reach an n-type drain layer at a low voltage when reverse bias is applied to the drain. It thus is possible to prevent thermal destruction caused by localized electrical field concentration. As a result, it is possible to increase ESD resistance. As it is sufficient to replace a photoresist mask, there is no increase in the number of processes.

## Claims

### Claim 1

A semiconductor device, comprising:
a second conductivity type well layer disposed on or in a surface layer of a first conductivity type semiconductor substrate;
a first conductivity type second well layer selectively disposed in a surface layer of the second conductivity type well layer;
a second conductivity type first offset layer and second conductivity type second offset layer spaced apart in a surface layer of the first conductivity type second well layer;
a second conductivity type high concentration layer, with an impurity concentration higher than that of the second offset layer, disposed in a surface layer of the second offset layer; and
a LOCOS oxide film disposed so as to enclose the high concentration layer, wherein
the diffusion depth of the second well layer below the high concentration layer is less than the diffusion depth of the second well layer below the LOCOS oxide film.

### Claim 2

A semiconductor device, comprising:
a first conductivity type well layer and second conductivity type well layer disposed on a first conductivity type semiconductor substrate;
a first conductivity type second well layer selectively disposed in a surface layer of the second conductivity type well layer;
a second conductivity type first offset layer and second conductivity type second offset layer spaced apart in a surface layer of the first conductivity type second well layer;
a second conductivity type source layer disposed in a surface layer of the first offset layer;
a second conductivity type drain layer disposed in a surface layer of the second offset layer;
a first conductivity type semiconductor layer disposed in contact with the source layer in a surface layer of the second well layer on the side opposite to that of the second offset layer;
a gate electrode disposed across a gate dielectric on the second well layer sandwiched by the first offset layer and second offset layer; and
a LOCOS oxide film, disposed so as to enclose the drain layer, disposed in contact with the gate dielectric, wherein
the second well layer is such that a bottom portion below the high concentration drain layer includes a region shallower than a bottom portion below the LOCOS oxide film.

### Claim 3 (depends on 1)

The semiconductor device according to claim 1, wherein the thickness of the second offset layer between the second well layer and high concentration drain layer is 0.8 μm or more.

### Claim 4

A method of manufacturing a semiconductor device including a first conductivity type well layer and second conductivity type well layer disposed on a first conductivity type semiconductor substrate and a first conductivity type second well layer selectively disposed in a surface layer of the second conductivity type well layer, the manufacturing method comprising:
a step of forming the first conductivity type well layer and second conductivity type well layer on or in a surface layer of the first conductivity type semiconductor substrate;
a step of ion implanting first conductivity type impurities using a photoresist mask including a first opening portion and a second opening portion enclosed by the first opening portion or formed so as to divide the first opening portion, and subsequently carrying out a drive-in process, thereby forming the second well layer including a region wherein the depth of a region corresponding to the second opening portion is less than the depth of a region corresponding to the first opening portion;
a step of forming a second conductivity type first offset layer in a surface layer of the second well layer;
a step of forming a second conductivity type second offset layer distanced from the first offset layer on a region of the second well layer with a small depth;
a step of forming a LOCOS oxide film including a third opening portion on the second offset layer;
a step of forming a gate dielectric so as to be in contact with the LOCOS oxide film on the second well layer sandwiched by the first offset layer and second offset layer and on the second offset layer;
a step of forming a gate electrode on the gate dielectric;
a step of forming a second conductivity type source layer in a surface layer of the first offset layer;
a step of ion implanting second conductivity type impurities into a surface layer of the second offset layer with the LOCOS oxide film as a mask, and carrying out a drive-in process, thereby forming a second conductivity type drain layer;
a step of forming a first conductivity type semiconductor layer in contact with the second well layer from the first offset layer surface; and
a step of forming a source electrode electrically connected to the source layer and semiconductor layer and a drain electrode electrically connected to the drain layer.

### Claim 5 (depends on 4)

The semiconductor device manufacturing method according to claim 4, wherein the impurities are boron.

### Claim 6 (depends on 4)

The semiconductor device manufacturing method according to claim 4, wherein the area of the second opening portion is regulated so as to bring the impurity concentration of the second well layer below the drain layer near to the impurity concentration of the second well layer below the LOCOS oxide film.

### Claim 7 (depends on 4)

The semiconductor device manufacturing method according to claim 4, wherein he first offset layer and second offset layer are formed simultaneously by an ion implantation of phosphorus impurities and a drive-in process.

### Claim 8 (depends on 4)

The semiconductor device manufacturing method according to claim 4, wherein he first conductivity type well layer or second conductivity type well layer is formed of an epitaxial layer, while the second conductivity type well layer or first conductivity type well layer is formed by diffusion.

### Claim 9 (depends on 2)

The semiconductor device according to claim 2, wherein the thickness of the second offset layer between the second well layer and high concentration drain layer is 0.8 μm or more.