# US 2014/0197490 A1 · Semiconductor device

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- Number: US 2014/0197490 A1
- Document ID: US20140197490A1
- Status: Published application
- Kind: A1
- Application number: 14/214,990
- Filed: 2014-03-16
- Published: 2014-07-17
- Earliest claimed: 2011-02-04
- Assignees: Renesas Electronics Corporation
- Applicants: Renesas Electronics Corporation
- Inventors: Kyoya NITTA
- Web page: https://patentgrep.com/patent/US20140197490A1

## CPC

- H10D 30/601: {having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs (lightly doped source or drain extensions for TFTs H10D30/6715)}
- H10D 30/0221: {having asymmetry in the channel direction, e.g. lateral high-voltage MISFETs having drain offset region or extended-drain MOSFETs [EDMOS]}
- H10D 30/603: {having asymmetry in the channel direction, e.g. lateral high-voltage MISFETs having drain offset region or extended drain IGFETs [EDMOS]}
- H10D 30/65: Lateral DMOS [LDMOS] FETs
- H10D 62/151: {of IGFETs (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713)}
- H10D 62/153: {Impurity concentrations or distributions}
- H10D 62/154: {Dispositions}
- H10D 62/157: {Impurity concentrations or distributions}
- H10D 62/158: {Dispositions}
- H10D 64/0112: {using conductive layers comprising silicides}
- H10D 64/254: {for lateral devices wherein the source or drain electrodes extend entirely through the semiconductor bodies, e.g. via-holes for back side contacts}
- H10D 64/257: {for lateral devices wherein the source or drain electrodes are characterised by top-view geometrical layouts, e.g. interdigitated, semi-circular, annular or L-shaped electrodes (source or drain electrodes of TFTs H10D30/673)}
- H10D 64/258: {characterised by the relative positions of the source or drain electrodes with respect to the gate electrode}
- H10P 14/412: {Deposition of metallic or metal-silicide materials}
- H10W 20/031: {of conductive parts of the interconnections}
- H10W 20/40: Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
- H10W 20/435: {Cross-sectional shapes or dispositions of interconnections}
- H10W 20/484: {Interconnections having extended contours, e.g. pads having mesh shape or interconnections comprising connected parallel stripes}
- H10W 20/495: {Capacitive arrangements or effects of, or between wiring layers}
- H10D 30/0212: {using self-aligned silicidation}
- H10D 62/371: {Inactive supplementary semiconductor regions, e.g. for preventing punch-through, improving capacity effect or leakage current}
- H10D 62/83: being Group IV materials, e.g. B-doped Si or undoped Ge
- H10D 64/021: {using multiple gate spacer layers, e.g. bilayered sidewall spacers}
- H10D 64/62: Electrodes ohmically coupled to a semiconductor
- H10D 64/663: {the additional layers comprising a silicide layer contacting the layer of silicon, e.g. polycide gates}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor device with improved characteristics is provided. The semiconductor device includes a LDMOS, a source plug electrically coupled to a source region of the LDMOS, a source wiring disposed over the source plug, a drain plug electrically coupled to a drain region of the LDMOS, and a drain wiring disposed over the drain plug. The structure of the source plug of the semiconductor device is devised. The semiconductor device is structured such that the drain plug is linearly disposed to extend in a direction Y, and the source plug includes a plurality of separated source plugs arranged at predetermined intervals in the direction Y. In this way, the separation of the source plug decreases an opposed area between the source plug and the drain plug, and can thus decrease the parasitic capacitance therebetween.

## Claims

### Claim 1

A semiconductor device, comprising:
(a) a laterally diffused MISFET, including:
(a1) a gate electrode disposed over a first surface of a semiconductor substrate via a gate insulating film to extend in a first direction; and
(a2) a source region disposed in the semiconductor substrate on one side of the gate electrode, and a drain region disposed in the semiconductor substrate on the other side of the gate electrode;
(b) a source contact disposed in a second region located on the one side of the gate electrode over the semiconductor substrate to be electrically coupled to the source region;
(c) a source wiring disposed over the source contact;
(d) a drain contact disposed in a first region located on the other side of the gate electrode over the semiconductor substrate to be electrically coupled to the drain region; and
(e) a drain wiring disposed over the drain contact,
wherein the drain contact is linearly disposed in the first region to extend in the first direction, and
wherein the source contact includes a plurality of separated source contacts arranged at predetermined intervals in the first direction in the second region.

### Claim 2 (depends on 1)

The semiconductor device according to claim 1, wherein a distance between the drain region and the other side end of the gate electrode is larger than that between the source region and one side end of the gate electrode.

### Claim 3 (depends on 1)

The semiconductor device according to claim 1, wherein a compound layer including a metal and a semiconductor for forming the semiconductor substrate is formed in the first region of the semiconductor substrate.

### Claim 4 (depends on 1)

The semiconductor device according to claim 1, wherein the semiconductor substrate includes an epitaxial layer, and the laterally diffused MISFET is formed over a main surface of the epitaxial layer.