# US 2014/0197488 A1 · Method of forming high voltage device

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- Number: US 2014/0197488 A1
- Document ID: US20140197488A1
- Status: Published application
- Kind: A1
- Application number: 14/212,081
- Filed: 2014-03-14
- Published: 2014-07-17
- Earliest claimed: 2010-01-05
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Company, Ltd.
- Inventors: Chih-Chang CHENG; Ruey-Hsin LIU; Chih-Wen YAO; Chia-Chin SHEN; Eric HUANG; Fu Chin YANG; Chun Lin TSAI; Chin Tuan HSIAO
- Web page: https://patentgrep.com/patent/US20140197488A1

## CPC

- H10D 84/83: of only insulated-gate FETs [IGFET]
- H10D 30/65: Lateral DMOS [LDMOS] FETs
- H10D 62/109: {Reduced surface field [RESURF] PN junction structures}
- H10D 62/157: {Impurity concentrations or distributions}
- H10D 62/393: {Body regions of DMOS transistors or IGBTs (cell layout of DMOS H10D62/127)}
- H10D 62/83: being Group IV materials, e.g. B-doped Si or undoped Ge
- H10D 64/111: {Field plates}
- H10D 64/516: {the thicknesses being non-uniform}
- H10D 64/62: Electrodes ohmically coupled to a semiconductor
- H10D 64/665: {the conductor comprising a layer of elemental metal contacting the insulator, e.g. tungsten or molybdenum (having lateral variation H10D64/671)}
- H10D 64/667: {the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN workfunction layers (having lateral variation H10D64/671)}
- H10D 64/685: {being perpendicular to the channel plane}
- H10D 64/691: {comprising metallic compounds, e.g. metal oxides or metal silicates (insulators comprising nitrogen H10D64/693)}
- H10D 64/693: {the insulator comprising nitrogen, e.g. nitrides, oxynitrides or nitrogen-doped materials}
- H10W 72/552: {comprising metals or metalloids, e.g. silver}
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/754: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A method of forming a device includes forming a buried well region of a first dopant type in a substrate. A well region of the first dopant type is formed over the buried well region. A first well region of a second dopant type is formed between the well region of the first dopant type and the buried well region of the first dopant type. A second well region of the second dopant type is formed in the well region of the first dopant type. An isolation structure is formed at least partially in the well region of the first dopant type. A first gate electrode is formed over the isolation structure and the second well region of the second dopant type.

## Claims

### Claim 1

A method of forming a device, the method comprising:
forming a buried well region of a first dopant type in a substrate;
forming a well region of the first dopant type over the buried well region;
forming a first well region of a second dopant type between the well region of the first dopant type and the buried well region of the first dopant type;
forming a second well region of the second dopant type in the well region of the first dopant type;
forming an isolation structure at least partially in the well region of the first dopant type; and
forming a first gate electrode over the isolation structure and the second well region of the second dopant type.

### Claim 2 (depends on 1)

The method of claim 1, further comprising:
forming a third well region of the second dopant type in the well region of the first dopant type, the third well region of the second dopant type being spaced from the second well region of the second dopant type; and
forming a second gate electrode between and over the second well region of the second dopant type and the third well region of the second dopant type.

### Claim 3 (depends on 2)

The method of claim 2, further comprising:
forming at least one fourth well region of the second dopant type in the well region of the first dopant type, the at least one fourth well region of the second dopant type being spaced from the third well region of the second dopant type; and
forming at least one third gate electrode between and over the third well region of the second dopant type and the at least one fourth well region of the second dopant type.

### Claim 4 (depends on 1)

The method of claim 1, further comprising:
forming a doped region of the first dopant type in the well region of the first dopant type.

### Claim 5 (depends on 4)

The method of claim 4, further comprising:
forming at least one metallic layer over and electrically coupled with the doped region of the first dopant type, wherein the at least one metallic layer extends along the direction of the channel under the first gate electrode.

### Claim 6 (depends on 5)

The method of claim 5, further comprising:
forming an electrode structure over the isolation structure, wherein the electrode structure is electrically coupled with the at least one metallic layer.

### Claim 7 (depends on 1)

The method of claim 1, wherein the first well region of the second dopant type is electrically coupled with the second well region of the second dopant type.

### Claim 8 (depends on 1)

The method of claim 1, further comprising:
forming at least one metallic layer over and electrically coupled with the first gate electrode, wherein the at least one metallic layer extends along a direction of a channel under the first gate electrode.

### Claim 9

A method of forming a device, the method comprising:
forming a well region of a first dopant type in a substrate;
forming a first well region of a second dopant type in the well region of the first dopant type;
forming an isolation structure at least partially in the well region of the first dopant type;
forming a first gate electrode over the isolation structure and the first well region of the second dopant type;
forming a doped region of the first dopant type in the well region of the first dopant type; and
forming an electrode structure over the isolation structure, the electrode structure being electrically coupled with the doped region.

### Claim 10 (depends on 9)

The method of claim 9, further comprising:
forming a buried well region of the first dopant type below the well region of the first dopant type; and
forming a second well region of the second dopant type between the well region of the first dopant type and the buried well region of the first dopant type.

### Claim 11 (depends on 10)

The method of claim 10, wherein the second well region of the second dopant type is electrically coupled with the first well region of the second dopant type.

### Claim 12 (depends on 9)

The method of claim 9, further comprising:
forming a third well region of the second dopant type in the well region of the first dopant type, the third well region of the second dopant type being spaced from the first well region of the second dopant type; and
forming a second gate electrode between and over the first well region of the second dopant type and the third well region of the second dopant type.

### Claim 13 (depends on 12)

The method of claim 12, further comprising:
forming at least one fourth well region of the second dopant type in the well region of the first dopant type, the at least one fourth well region of the second dopant type being spaced from the third well region of the second dopant type; and
forming at least one third gate electrode between and over the third well region of the second dopant type and the at least one fourth well region of the second dopant type.

### Claim 14 (depends on 9)

The method of claim 9, further comprising:
forming at least one metallic layer over and electrically coupled with the first gate electrode, wherein the at least one metallic layer extends along a direction of a channel under the first gate electrode.

### Claim 15

A method of forming a transistor, comprising:
forming a well region of a first dopant type in a substrate, the well region of the first dopant type having a first edge and a second edge;
forming a first well region of a second dopant type in the well region of the first dopant type;
forming an isolation structure at least partially in the well region of the first dopant type, the isolation structure being between the first well region of the second dopant type and the first edge of the well region of the first dopant type;
forming a first gate electrode over the isolation structure and the first well region of the second dopant type; and
forming a doped region of the first dopant type in the well region of the first dopant type, the doped region functioning as a drain region of the transistor and being between the isolation structure and the first edge of the well region of the first dopant type, the well region of the first dopant type being free from having another drain region between the isolation structure and the second edge of the well region of the first dopant type.

### Claim 16 (depends on 15)

The method of claim 15, further comprising:
forming a buried well region of the first dopant type below the well region of the first dopant type; and
forming a second well region of the second dopant type between the well region of the first dopant type and the buried well region of the first dopant type.

### Claim 17 (depends on 16)

The method of claim 16, wherein the second well region of the second dopant type is electrically coupled with the first well region of the second dopant type.

### Claim 18 (depends on 15)

The method of claim 15, further comprising:
forming a third well region of the second dopant type in the well region of the first dopant type, the third well region of the second dopant type being spaced from the first well region of the second dopant type; and
forming a second gate electrode between and over the first well region of the second dopant type and the third well region of the second dopant type.

### Claim 19 (depends on 18)

The method of claim 18, further comprising:
forming at least one fourth well region of the second dopant type in the well region of the first dopant type, the at least one fourth well region of the second dopant type being spaced from the third well region of the second dopant type; and
forming at least one third gate electrode between and over the third well region of the second dopant type and the at least one fourth well region of the second dopant type.

### Claim 20 (depends on 15)

The method of claim 15, further comprising:
forming at least one metallic layer over and electrically coupled with the first gate electrode, wherein the at least one metallic layer extends along a direction of a channel under the first gate electrode.