# US 2014/0197487 A1 · Ldmos power semiconductor device and manufacturing method of the same

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- Number: US 2014/0197487 A1
- Document ID: US20140197487A1
- Status: Published application
- Kind: A1
- Application number: 14/151,527
- Filed: 2014-01-09
- Published: 2014-07-17
- Earliest claimed: 2013-01-11
- Assignees: STMicroelectronics S.r.l.
- Applicants: STMicroelectronics S.r.l.
- Inventors: Salvatore Cascino; Leonardo Gervasi; Antonello Santangelo
- Web page: https://patentgrep.com/patent/US20140197487A1

## CPC

- H10D 30/0281: {of lateral DMOS [LDMOS] FETs}
- H10D 30/0285: {using formation of insulating sidewall spacers}
- H10D 30/0293: {using formation of insulating sidewall spacers}
- H10D 30/0295: {using recessing of the source electrodes}
- H10D 30/66: Vertical DMOS [VDMOS] FETs
- H10D 62/157: {Impurity concentrations or distributions}
- H10D 62/159: {Shapes}
- H10D 64/112: {comprising multiple field plate segments}
- H10D 64/117: {Recessed field plates, e.g. trench field plates or buried field plates}
- H10D 64/256: {for lateral devices wherein the source or drain electrodes are recessed in semiconductor bodies (source or drain electrodes of TFTs H10D30/673)}
- H10D 84/013: {Manufacturing their source or drain regions, e.g. silicided source or drain regions}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/83: of only insulated-gate FETs [IGFET]
- H10P 30/222: {characterised by the angle between the ion beam and the crystal planes or the main crystal surface (characterised by the angle between the ion beam and the mask H10P30/221)}
- H10D 30/603: {having asymmetry in the channel direction, e.g. lateral high-voltage MISFETs having drain offset region or extended drain IGFETs [EDMOS]}
- H10D 62/109: {Reduced surface field [RESURF] PN junction structures}
- H10D 62/111: {Multiple RESURF structures, e.g. double RESURF or 3D-RESURF structures}
- H10D 62/393: {Body regions of DMOS transistors or IGBTs (cell layout of DMOS H10D62/127)}
- H10D 64/025: {forming recessed gates, e.g. by using local oxidation}
- H10D 64/254: {for lateral devices wherein the source or drain electrodes extend entirely through the semiconductor bodies, e.g. via-holes for back side contacts}
- H10D 64/663: {the additional layers comprising a silicide layer contacting the layer of silicon, e.g. polycide gates}
- H10D 84/016: {the components including vertical IGFETs}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

An electronic semiconductor device comprising: a semiconductor body, having a first side and a second side opposite to one another and including a first structural region facing the second side, and a second structural region extending over the first structural region and facing the first side; a body region extending in the second structural region at the first side; a source region extending inside the body region; an LDD region facing the first side of the semiconductor body; and a gate electrode. The device comprises: a trench dielectric region extending through the second structural region a first trench conductive region immediately adjacent to the trench dielectric region; and a second trench conductive region in electrical contact with the body region and with the source region. An electrical contact at the second side of the semiconductor body is in electrical contact with the drain region via the first structural region.

## Claims

### Claim 1

An electronic semiconductor device comprising:
a semiconductor body having a first side and a second side opposite to one another along a first direction and including a first structural region, which faces the second side and has a first conductivity; and a second structural region which extends over the first structural region, faces the first side, and has a second conductivity opposite to the first conductivity;
a body region having the second conductivity and extending in the second structural region at the first side;
a source region having the first conductivity, extending within the body region and facing the first side;
a drain region having the first conductivity and facing the first side of the semiconductor body;
a gate electrode extending over a portion of the first side of the semiconductor body between the source region and the drain region;
a first trench which extends through the second structural region and houses a trench dielectric region and a first trench conductive region; and
a second trench which extends through part of the second structural region inside the body region, said second trench housing a second trench conductive region in electrical contact with the body region and with the source region,
wherein the drain region extends through the second structural region, electrically contacts the first structural region, and is arranged between, and in direct contact with, the body region and the trench dielectric region, said first and second trench conductive regions being electrically coupled to one another.

### Claim 2 (depends on 1)

The device according to claim 1, wherein the first trench extends throughout a thickness of the second structural region and through part of the first structural region and terminates in the first structural region.

### Claim 3 (depends on 1)

The device according to claim 1, wherein the trench dielectric region extends on an inner wall and on a bottom of the first trench.

### Claim 4 (depends on 1)

The device according to claim 1, wherein the first trench conductive region extends throughout a thickness of the second structural region and is electrically insulated from the first and second structural regions by the trench dielectric region.

### Claim 5 (depends on 1)

The device according to claim 1, wherein the first trench conductive region extends only for a portion of a thickness of the second structural region and is electrically insulated from the first and second structural regions by the trench dielectric region.

### Claim 6 (depends on 1)

The device according to claim 1, wherein the trench dielectric region has a first thickness at a first depth value in the semiconductor body and a second thickness, greater than the first thickness, at a second depth value, greater than the first depth value, in the semiconductor body.

### Claim 7 (depends on 6)

The device according to claim 6, wherein the trench dielectric region furthermore has a third thickness, greater than the second thickness, at a third depth value, greater than the second depth value, in the semiconductor body.

### Claim 8 (depends on 1)

The device according to claim 1, wherein the drain region is an implanted region of a light-doped-drain type.

### Claim 9 (depends on 1)

The device according to claim 1, further comprising:
a conductive layer that electrically couples the first and second trench conductive regions to one another and extends on a top side of the gate electrode; and
a gate dielectric layer which extends over the first side of the semiconductor body between the second structural region and the gate electrode, wherein the gate electrode includes: a conductive gate region in contact with the gate dielectric layer, and an insulating gate region covering the conductive gate region and electrically insulating a top side of the conductive gate region from the conductive layer.

### Claim 10 (depends on 1)

The device according to claim 1, further comprising an enriched region, which has the second conductivity and extends in the body region, said second trench conductive region being in electrical contact with the body region via the enriched region.

### Claim 11 (depends on 1)

The device according to claim 1, further comprising a first spacer and a second spacer, which are made of dielectric material and are arranged on the first side of the semiconductor body at respective opposite sides of the gate electrode, wherein the second trench conductive region extends alongside the gate electrode, and is electrically insulated from the gate electrode by the second spacer.

### Claim 12

A method for manufacturing an electronic semiconductor device, comprising:
defining a first structural region having a first conductivity in a substrate, the first structural region including a first side and a second side;
forming, on the first side of the first structural region, a second structural region having a first side exposed and having a second conductivity opposite to the first conductivity;
forming a body region, having the second conductivity, in the second structural region at the first side of the second structural region;
forming a source region, having the first conductivity, within the body region and facing the first side of the second structural region;
forming a drain region, having the first conductivity, facing the first side of the second structural region; and
forming a gate electrode on the first side of the structural region, between the source region and the drain region,
removing selective portions of the second structural region so as to form a through hole, which extends through the second structural region throughout a thickness of the second structural region;
removing selective portions of the first structural region exposed through said through hole so as to form a first trench, which extends through the second structural region;
forming a trench dielectric region inside the first trench;
forming a first trench conductive region inside the trench dielectric region;
removing selective portions of the second structural region in the body region so as to form a second trench;
forming a second trench conductive region inside the second trench so that the second trench conductive region is in electrical contact with the body region and with the source region; and
electrically coupling together said first and second trench conductive regions,
wherein forming the drain region includes forming the drain region between, and in direct contact with, the body region and the trench dielectric region and extending in depth through the second structural region coming into electrical contact with, the first structural region.

### Claim 13 (depends on 12)

The method according to claim 12, wherein the step of forming the trench dielectric region includes depositing one or more dielectric materials on an inner wall and on a bottom of the first trench.

### Claim 14 (depends on 12)

The method according to claim 12, wherein forming the trench dielectric region includes:
depositing a first layer of filling dielectric on an inner wall and on a bottom of the first trench; and
depositing a second layer of filling dielectric in the trench, the second layer of filling dielectric covering the first layer of filling dielectric and extending alongside the gate electrode.

### Claim 15 (depends on 14)

The method according to claim 14, wherein forming the trench dielectric region further includes:
depositing a third layer of filling dielectric in the first trench;
removing selectively the third layer of filling dielectric except for portions of the third layer of filling dielectric which extend in regions corresponding to walls of the first trench close to the bottom of the first trench so that the trench dielectric region has a first thickness at a first depth value and a second thickness, greater than the first thickness, at a second depth value greater than the first depth value.

### Claim 16 (depends on 12)

The method according to claim 12, wherein forming the drain region includes performing a masked slanted implantation of dopant species, which have the first conductivity, in the second structural region, such that the drain regions extends adjacent to a wall of the first trench.

### Claim 17 (depends on 16)

The method according to claim 16, wherein performing said masked slanted implantation includes performing said masked slanted implantation at an implantation angle between ±10° and ±15° with respect to a direction of main extension of the first trench, said implantation having an implantation dose ranging from approximately 1·1013 cm−2 to approximately 5·1013 cm−2.

### Claim 18 (depends on 16)

The method according to claim 16, wherein forming the drain region further includes performing a thermal annealing that diffuses the dopant species and forms the drain region as a light-doped-drain region.

### Claim 19 (depends on 12)

The method according to claim 12, further comprising forming a gate dielectric layer on the first side of the second structural region, between the second structural region and the gate electrode, wherein forming the gate electrode includes the substeps of: forming a conductive gate region on the gate dielectric layer, and forming an insulating gate region on the conductive gate region so as to electrically insulate the conductive gate region.

### Claim 20 (depends on 12)

The method according to claim 12, further comprising forming an enriched region, having the second conductivity, in the body region, wherein forming said second trench conductive region comprising forming said second trench conductive region in electrical contact with the enriched region.

### Claim 21 (depends on 20)

The method according to claim 20, further comprising forming a first spacer and a second spacer, made of dielectric material, on the first side of the second structural region, at respective opposite sides of the gate electrode, wherein forming the second trench conductive region comprises forming the second trench conductive region alongside the gate electrode, electrically insulated from the gate electrode by the second spacer.

### Claim 22

An electronic semiconductor device comprising:
a bridge of first and second transistors in a semiconductor body having a first side and a second side opposite to one another along a first direction and including a first structural region that faces the second side and has a first conductivity, wherein the first transistor includes:
a second structural region which extends over the first structural region, faces the first side, and has a second conductivity opposite to the first conductivity;
a first body region having the second conductivity and extending in the second structural region at the first side;
a first source region having the first conductivity, extending within the first body region and facing the first side;
a first drain region having the first conductivity and facing the first side of the semiconductor body;
a first gate electrode extending over a portion of the first side of the semiconductor body between the first source region and the first drain region;
a first trench which extends through the second structural region and houses a trench dielectric region and a first trench conductive region; and
a second trench which extends through part of the second structural region inside the first body region, said second trench housing a second trench conductive region in electrical contact with the first body region and with the first source region,
wherein the first drain region extends through the second structural region, electrically contacts the first structural region, and is arranged between, and in direct contact with, the first body region and the trench dielectric region, said first and second trench conductive regions being electrically coupled to one another.

### Claim 23 (depends on 22)

The device according to claim 22, wherein the second transistor includes:
a third structural region which extends over the first structural region, faces the first side, is positioned laterally with respect to the second structural region, and has the second conductivity;
a second body region having the second conductivity and extending in the third structural region at the first side;
a second source region having the first conductivity, extending within the second body region and facing the first side;
a second drain region having the first conductivity and facing the first side of the semiconductor body;
a second gate electrode extending over a portion of the first side of the semiconductor body between the second source region and the second drain region; and
a conductive via electrically contacting the second source region and extending through the third structural region into electrical contact with the first structural region.

### Claim 24 (depends on 22)

The device according to claim 22, further comprising a metal layer contacting the second side of the semiconductor body and extending from at least a position directly below the conductive via to at least a position directly below the first drain region.