# US 2014/0197486 A1 · Power integrated circuit including series-connected source substrate and drain substrate power mosfets

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- Number: US 2014/0197486 A1
- Document ID: US20140197486A1
- Status: Published application
- Kind: A1
- Application number: 13/563,923
- Filed: 2012-08-01
- Published: 2014-07-17
- Earliest claimed: 2011-08-04
- Assignees: Texas Instruments Incorporated
- Inventors: Christopher Boguslaw Kocon; Marie Denison; Taylor Efland
- Web page: https://patentgrep.com/patent/US20140197486A1

## CPC

- H10D 84/83: of only insulated-gate FETs [IGFET]
- H10D 30/603: {having asymmetry in the channel direction, e.g. lateral high-voltage MISFETs having drain offset region or extended drain IGFETs [EDMOS]}
- H10D 30/65: Lateral DMOS [LDMOS] FETs
- H10D 30/66: Vertical DMOS [VDMOS] FETs
- H10D 30/663: {having both source contacts and drain contacts on the same surface, i.e. up-drain VDMOS}
- H10D 64/112: {comprising multiple field plate segments}
- H10D 64/117: {Recessed field plates, e.g. trench field plates or buried field plates}
- H10D 84/141: {VDMOS having built-in components}
- H10D 62/111: {Multiple RESURF structures, e.g. double RESURF or 3D-RESURF structures}
- H10D 62/115: {Dielectric isolations, e.g. air gaps}
- H10D 62/127: {of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs}
- H10D 64/256: {for lateral devices wherein the source or drain electrodes are recessed in semiconductor bodies (source or drain electrodes of TFTs H10D30/673)}
- H10D 64/516: {the thicknesses being non-uniform}
- H10D 64/663: {the additional layers comprising a silicide layer contacting the layer of silicon, e.g. polycide gates}
- H10D 84/856: {the complementary IGFETs having different architectures than each other, e.g. high-voltage and low-voltage CMOS}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A semiconductor device containing a high voltage MOS transistor with a drain drift region over a lower drain layer and channel regions laterally disposed at the top surface of the substrate. RESURF trenches cut through the drain drift region and body region parallel to channel current flow. The RESURF trenches have dielectric liners and electrically conductive RESURF elements on the liners. Source contact metal is disposed over the body region and source regions. A semiconductor device containing a high voltage MOS transistor with a drain drift region over a lower drain layer, and channel regions laterally disposed at the top surface of the substrate. RESURF trenches cut through the drain drift region and body region perpendicular to channel current flow. Source contact metal is disposed in a source contact trench and extended over the drain drift region to provide a field plate.

## Claims

### Claim 1

A semiconductor device, comprising:
a semiconductor substrate;
a high voltage metal oxide semiconductor (MOS) transistor, including:
a heavily doped lower drain layer in said substrate, said lower drain layer having a first conductivity type with an average doping density greater than 1×1019 cm−3;
a drain drift region disposed over said lower drain layer, said drain drift region having said first conductivity type with an average doping density between 1×1015 cm−3 and 3×1018 cm−3;
a body region disposed in said substrate extending to a top surface of said substrate and contacting said drain drift region, said body region having a second conductivity type opposite from said first conductivity type;
channel regions in said body region at a top surface of said body region abutting said drain drift region;
source regions in said substrate abutting said channel regions opposite from said drain drift region, said source regions having said first conductivity type, so that channel current in said channel flows in a direction perpendicular to a boundary between said drain drift region and said channel regions;
a gate dielectric layer over said channel regions;
a gate over said gate dielectric layer;
a plurality of RESURF trenches in said substrate cutting through said drain drift region, said body region and said source regions, so that sidewalls of said RESURF trenches are parallel to said direction of channel current flow within fabrication tolerances used to form said semiconductor device, said RESURF trenches including:
RESURF dielectric liners on said sidewalls of said RESURF trenches; and
electrically conductive RESURF conductive elements on said RESURF dielectric liners;
source contact metal disposed over said body region, said source contact metal being electrically connected to said body region and said source regions; and
drain contact metal, said drain contact metal being electrically connected to said lower drain layer.

### Claim 2 (depends on 1)

The semiconductor device of claim 1, in which said source contact metal is disposed in a source contact trench in said substrate, such that:
said source contact trench extends from said top surface of said substrate down to said body region and to said RESURF conductive elements, so that said source contact metal makes electrical contact to said body region and to said RESURF conductive elements at a bottom surface of said source contact trench; and
said source contact trench extends laterally to said source regions, so that said source contact metal makes electrical contact to said source regions at sidewalls of said source contact trench.

### Claim 3 (depends on 1)

The semiconductor device of claim 1, in which:
said lower drain layer extends to a bottom surface of said substrate; and
said drain contact metal is disposed at a bottom surface of said lower drain layer in direct contact with said lower drain layer.

### Claim 4 (depends on 1)

The semiconductor device of claim 1, in which said RESURF trenches further include RESURF semiconductor regions or said second conductivity type disposed in bottom portions of said RESURF trenches, so that said RESURF dielectric liners are disposed between said RESURF semiconductor regions and said RESURF conductive elements.

### Claim 5 (depends on 1)

The semiconductor device of claim 1, further including vertical heavily doped drain risers in said substrate adjacent to said RESURF trenches opposite from said body region, said drain risers laterally contacting said drain drift region and extending from said lower drain layer to a top surface of said drain drift region, said drain risers having said first conductivity type with an average doping density greater than 1×1019 cm−3, such that said drain risers are free of direct contact to said drain contact metal.

### Claim 6 (depends on 5)

The semiconductor device of claim 5, in which said drain risers are laterally separated from said RESURF trenches by a distance between 0.5 microns and 3 microns.

### Claim 7 (depends on 1)

The semiconductor device of claim 1, in which:
said lower drain layer extends laterally past said RESURF trenches and said drain drift region;
heavily doped drain sinkers are disposed at a periphery of said transistor and making contact with said lower drain layer, said drain sinkers being laterally separated from said RESURF trenches and said drain drift region by dielectric isolation elements, said drain sinkers having said first conductivity type with an average doping density greater than 1×1019 cm−3; and
said drain contact metal is disposed over said drain sinkers such that said drain sinkers are electrically coupled to said drain contact metal.

### Claim 8 (depends on 1)

The semiconductor device of claim 1, in which said gate is extended over said drain drift region, said gate being separated from a top surface of said drain drift region by a field plate dielectric layer.

### Claim 9 (depends on 1)

The semiconductor device of claim 1, in which said source contact metal is extended over said drain drift region, said source contact metal being separated from a top surface of said drain drift region by a field plate dielectric layer.

### Claim 10 (depends on 1)

The semiconductor device of claim 1, in which said RESURF conductive elements are electrically coupled to said source contact metal.

### Claim 11 (depends on 9)

The semiconductor device of claim 9, in which said RESURF conductive elements are electrically coupled to said source contact metal through resistors having impedances of at least 2 ohms.

### Claim 12 (depends on 1)

The semiconductor device of claim 1, further including a second transistor in said substrate.

### Claim 13 (depends on 1)

The semiconductor device of claim 1, in which:
said RESURF trenches are between 2 and 3 microns deep and between 2 and 3 microns wide, with a spacing between adjacent said RESURF trenches of 3 to 5 microns; and
an average doping density of said drain drift region between said RESURF trenches is between 1×1016 cm-3 and 3×1016 cm-3.

### Claim 14

A semiconductor device, comprising:
a semiconductor substrate;
a high voltage MOS transistor, including:
a heavily doped lower drain layer in said substrate, said lower drain layer having a first conductivity type with an average doping density greater than 1×1020 cm−3;
a drain drift region disposed over said lower drain layer, said drain drift region having said first conductivity type with an average doping density between 1×1016 cm−3 and 1×1018 cm−3;
a body region disposed in said substrate extending to a top surface of said substrate and contacting said drain drift region, said body region having a second conductivity type opposite from said first conductivity type;
channel regions in said body region at a top surface of said body region abutting said drain drift region;
source regions in said substrate abutting said channel regions opposite from said drain drift region, said source regions having said first conductivity type, so that channel current in said channel flows in a direction perpendicular to a boundary between said drain drift region and said channel regions;
a gate dielectric layer over said channel regions;
a gate over said gate dielectric layer;
a plurality of RESURF trenches in said substrate cutting through said drain drift region and said body region, so that sidewalls of said RESURF trenches are perpendicular to said direction of channel current flow within fabrication tolerances used to form said semiconductor device, said RESURF trenches including:
RESURF dielectric liners on said sidewalls of said RESURF trenches; and
electrically conductive RESURF conductive elements on said RESURF dielectric liners;
source contact metal disposed over said body region and in a source contact trench in said substrate, such that:
said source contact trench extends from said top surface of said substrate down to said body region and to said RESURF conductive elements, so that said source contact metal makes electrical contact to said body region and to said RESURF conductive elements at a bottom surface of said source contact trench;
said source contact trench extends laterally to said source regions, so that said source contact metal makes electrical contact to said source regions at sidewalls of said source contact trench; and
said source contact metal is extends over said drain drift region and separated from a top surface of said drain drift region by a field plate dielectric layer; and
drain contact metal, said drain contact metal being electrically connected to said lower drain layer.

### Claim 15 (depends on 14)

The semiconductor device of claim 14, in which:
said lower drain layer extends to a bottom surface of said substrate; and
said drain contact metal is disposed at a bottom surface of said lower drain layer in direct contact with said lower drain layer.

### Claim 16 (depends on 14)

The semiconductor device of claim 14, in which said RESURF trenches further include RESURF semiconductor regions or said second conductivity type disposed in bottom portions of said RESURF trenches, so that said RESURF dielectric liners are disposed between said RESURF semiconductor regions and said RESURF conductive elements.

### Claim 17 (depends on 14)

The semiconductor device of claim 14, in which:
said lower drain layer extends laterally past said RESURF trenches and said drain drift region;
heavily doped drain sinkers are disposed at a periphery of said transistor and making contact with said lower drain layer, said drain sinkers being laterally separated from said RESURF trenches and said drain drift region by dielectric isolation elements, said drain sinkers having said first conductivity type with an average doping density greater than 1×1019 cm−3; and
said drain contact metal is disposed over said drain sinkers such that said drain sinkers are electrically coupled to said drain contact metal.

### Claim 18 (depends on 14)

The semiconductor device of claim 14, in which said RESURF conductive elements are electrically coupled to said source contact metal.

### Claim 19 (depends on 18)

The semiconductor device of claim 18, in which said RESURF conductive elements are electrically coupled to said source contact metal through resistors having impedances of at least 2 ohms.

### Claim 20 (depends on 14)

The semiconductor device of claim 14, further including a second transistor in said substrate.