# US 2014/0197485 A1 · Semiconductor device and manufacturing method thereof > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2014/0197485 A1 - Document ID: US20140197485A1 - Status: Published application - Kind: A1 - Application number: 13/917,989 - Filed: 2013-06-14 - Published: 2014-07-17 - Earliest claimed: 2013-01-11 - Assignees: Kabushiki Kaisha Toshiba - Applicants: Kabushiki Kaisha Toshiba - Inventors: Masafumi HAMAGUCHI - Web page: https://patentgrep.com/patent/US20140197485A1 ## CPC - H10D 64/01: Manufacture or treatment - H10D 30/60: Insulated-gate field-effect transistors [IGFET] (H10D30/40 takes precedence) - H10D 62/151: {of IGFETs (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713)} - H10D 64/01326: {Aspects related to lithography, isolation or planarisation of the conductor} - H10D 64/258: {characterised by the relative positions of the source or drain electrodes with respect to the gate electrode} - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES ## Abstract A semiconductor device includes a substrate, and a gate electrode formed on the substrate on a gate insulation film. The semiconductor device also includes a source diffusion layer and a drain diffusion layer which are formed on the substrate where the gate electrode is sandwiched between the source diffusion layer and the drain diffusion layer, one or more source contacts formed on the source diffusion layer; and one or more drain contacts formed on the drain diffusion layer. At least one of the source contacts and the drain contacts includes a first contact region having a first size and a second contact region having a second size larger than the first size on the same source diffusion layer or on the same drain diffusion layer. ## Claims ### Claim 1 A semiconductor device, comprising: a substrate; a gate electrode formed on the substrate on a gate insulation film; a source diffusion layer and a drain diffusion layer which are formed within the substrate sandwiching the gate electrode therebetween; one or more source contacts formed on the source diffusion layer; and one or more drain contacts formed on the drain diffusion layer, wherein at least one of the source contacts and the drain contacts includes a first contact region having a first size and a second contact region having a second size larger than the first size on the same source diffusion layer or on the same drain diffusion layer. ### Claim 2 (depends on 1) The semiconductor device according to claim 1, wherein a resistance of the second contact region is 0.9 times to 1.1 times a resistance of N (N being an integer of 2 or more) first contact regions which are connected to each other in parallel. ### Claim 3 (depends on 1) The semiconductor device according to claim 1, wherein the semiconductor device belongs to the 28 nm generation or the generation following the 28 nm generation. ### Claim 4 (depends on 1) The semiconductor device according to claim 1, wherein the first contact region and the second contact region are alternately arranged on at least one of the source diffusion layer and the drain diffusion layer. ### Claim 5 (depends on 1) The semiconductor device according to claim 1, wherein the first contact region formed on the source diffusion layer is arranged adjacent to the second contact region formed on the drain diffusion layer. ### Claim 6 (depends on 5) The semiconductor device according to claim 5, wherein the second contact region formed on the source diffusion layer is arranged adjacent to the first contact formed on the drain diffusion layer. ### Claim 7 (depends on 1) The semiconductor device according to claim 1, wherein the first contact region formed on the source diffusion layer is arranged adjacent to the second contact region formed on the drain diffusion layer, and the second contact region formed on the source diffusion layer is arranged adjacent to the first contact formed on the drain diffusion layer. ### Claim 8 (depends on 1) The semiconductor device according to claim 1, wherein a third contact region having a third size greater than the second size is formed on the same source diffusion layer or on the same drain diffusion layer. ### Claim 9 A manufacturing method of a semiconductor device, comprising: preparing design data for manufacturing a semiconductor device which comprises a first contact region having a first size; preparing a photo mask based on the design data, wherein N (N being an integer of 2 or more) first contact regions are replaced with one second contact region having a second size greater than the first size; and forming a semiconductor device having the first contact region and the second contact region formed on at least one of a common source diffusion layer and a common drain diffusion layer using the photo mask. ### Claim 10 (depends on 9) The manufacturing method of claim 9, wherein the first contact region formed on the common source diffusion layer is arranged adjacent to the second contact region formed on the common drain diffusion layer. ### Claim 11 (depends on 10) The manufacturing method of claim 10, wherein the second contact region formed on the common source diffusion layer is arranged adjacent to the first contact formed on the common drain diffusion layer. ### Claim 12 (depends on 9) The manufacturing method of claim 9, further comprising: preparing the photo mask to include a third contact region having a third size greater than the second size, and forming the third contact region on at least one of the common source diffusion layer and the common drain diffusion layer using the photo mask. ### Claim 13 (depends on 9) The manufacturing method of claim 9, wherein the first contact region and the second contact region are alternately arranged on at least one of the common source diffusion layer and the common drain diffusion layer. ### Claim 14 (depends on 9) The manufacturing method of claim 9, wherein a resistance of the second contact region is 0.9 times to 1.1 times a resistance of N (N being an integer of 2 or more) first contact regions which are connected to each other in parallel. ### Claim 15 A manufacturing method of a semiconductor device, comprising: preparing design data for manufacturing a semiconductor device which comprises a first contact having a first size; preparing a photo mask based on the design data, wherein N (N being an integer of 2 or more) first contact regions are replaced with a single second contact region having a second size larger than the first size, and having a resistance from 0.9 times to 1.1 times a resistance of the N first contact regions which are connected to each other in parallel; and forming the semiconductor device having the second contact region on at least one of a source diffusion layer and a drain diffusion layer using the photo mask. ### Claim 16 (depends on 15) The manufacturing method of claim 15, wherein the N first contact regions and the second contact region are alternately arranged on at least one of the source diffusion layer and the drain diffusion layer. ### Claim 17 (depends on 15) The manufacturing method of claim 15, wherein the first contact region formed on the source diffusion layer is arranged adjacent to the second contact region formed on the drain diffusion layer. ### Claim 18 (depends on 17) The manufacturing method of claim 17, wherein the second contact region formed on the source diffusion layer is arranged adjacent to the first contact formed on the drain diffusion layer. ### Claim 19 (depends on 15) The manufacturing method of claim 15, wherein the N first contact regions and the second contact region are arranged on at least one of the source diffusion layer and the drain diffusion layer, respectively. ### Claim 20 (depends on 15) The manufacturing method of claim 15, further comprising: preparing the photo mask to include a third contact region having a third size greater than the second size, and forming the third contact region on at least one of the source diffusion layer and the drain diffusion layer using the photo mask.