# US 2014/0197479 A1 · Semiconductor device having dual parallel channel structure and method of fabricating the same

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- Number: US 2014/0197479 A1
- Document ID: US20140197479A1
- Status: Published application
- Kind: A1
- Application number: 13/960,333
- Filed: 2013-08-06
- Published: 2014-07-17
- Earliest claimed: 2013-01-14
- Assignees: Samsung Electronics Co., Ltd.
- Applicants: Samsung Electronics Co., Ltd.
- Inventors: Chang-yong UM; Jai-kwang SHIN
- Web page: https://patentgrep.com/patent/US20140197479A1

## CPC

- H10D 30/668: {having trench gate electrodes, e.g. UMOS transistors}
- H10D 30/0297: {using recessing of the gate electrodes, e.g. to form trench gate electrodes}
- H10D 62/154: {Dispositions}
- H10D 62/393: {Body regions of DMOS transistors or IGBTs (cell layout of DMOS H10D62/127)}
- H10D 64/518: {characterised by their lengths or sectional shapes}
- H10D 64/519: {characterised by their top-view geometrical layouts}
- H10D 84/141: {VDMOS having built-in components}
- H10D 64/0133: {at least part of the entire electrode being a sidewall spacer, being formed by transformation under a mask or being formed by plating at a sidewall}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A semiconductor device may include a substrate having a drift region doped to a first conduction type. A trench may be etched into an upper surface of the substrate. A gate may be arranged along side walls of the trench. A gate oxide layer may be between the side walls of the trench and gate and between a bottom surface of the trench and gate. A first source region of the first conduction type may be on the upper surface of the substrate. A second source region of the first conduction type may be on the bottom surface of the trench. A first well region may be between the first source region and drift region, and a second well region may be between the second source region and drift region, the first and second well regions being doped to a second conduction type (electrically opposite to the first conduction type).

## Claims

### Claim 1

A semiconductor device, comprising:
a substrate including a drift region, the drift region doped to a first conduction type;
a trench in an upper surface of the substrate;
a gate arranged along side walls of the trench;
a gate oxide layer between the side walls of the trench and the gate and between a bottom surface of the trench and the gate;
a first source region on the upper surface of the substrate, the first source region being of the first conduction type;
a second source region on the bottom surface of the trench, the second source region being of the first conduction type;
a first well region between the first source region and the drift region; and
a second well region between the second source region and the drift region, the first and second well regions doped to a second conduction type, the second conduction type being electrically opposite to the first conduction type.

### Claim 2 (depends on 1)

The semiconductor device as claimed in claim 1, further comprising:
a drain electrode on a lower surface of the substrate;
a source electrode on the substrate and in the trench so as to be electrically connected to the first and second source regions; and
an interlayer insulating layer covering the gate and the gate oxide layer such that the gate and the gate oxide layer do not contact the source electrode.

### Claim 3 (depends on 2)

The semiconductor device as claimed in claim 2, further comprising:
a first ohmic contact layer between the first well region and the source electrode so as to provide ohmic contact between the source electrode and the first source region; and
a second ohmic contact layer in a central portion of the second source region so as to provide ohmic contact between the source electrode and the second source region,
wherein the first and second ohmic contact layers are doped to the second conduction type.

### Claim 4 (depends on 3)

The semiconductor device as claimed in claim 3, wherein
the first ohmic contact layer is on the first well region so as to be adjacent to the first source region, and
the second ohmic contact layer is on the second well region so as to be adjacent to the second source region.

### Claim 5 (depends on 1)

The semiconductor device as claimed in claim 1, wherein the substrate includes a lower region, the drift region being on the lower region,
the lower region and the drift region are doped to the first conduction type, a doping concentration of the drift region being lower than that of the lower region, and the lower region of the substrate is N+-doped and the drift region is N-doped.

### Claim 6 (depends on 1)

The semiconductor device as claimed in claim 1, wherein the gate is circular, polygonal ring-shaped, or linear-shaped.

### Claim 7 (depends on 1)

The semiconductor device as claimed in claim 1, wherein the gate oxide layer exposes a central portion of the bottom surface of the trench.

### Claim 8 (depends on 1)

The semiconductor device as claimed in claim 1, wherein
the second source region is partially present on the bottom surface of the trench, the second source region surrounding a central portion of the bottom surface of the trench,
the gate overlaps an edge of the second source region, and
the first source region faces an upper portion of a side surface of the gate.

### Claim 9 (depends on 1)

The semiconductor device as claimed in claim 1, wherein the first and second source regions are N+-doped, and the first and second well regions are P-doped.

### Claim 10 (depends on 1)

The semiconductor device as claimed in claim 1, wherein the first well region is below an entirety of the first source region,
the second well region entirely surrounds a bottom surface and side walls of the second source region, and
the gate overlaps a part of the second well region that surrounds the side walls of the second source region.

### Claim 11

A method of fabricating a semiconductor device, comprising:
vertically etching an upper surface of a substrate to form a trench, the substrate including a lower region and a drift region on the lower region, the lower region and the drift region of the substrate being doped to a first conduction type;
doping the upper surface of the substrate and a bottom surface of the trench to a second conduction type to form a first well region and a second well region;
forming a first source region and a second source region on the first well region and the second well region, respectively, the first and second source regions being doped to the first conduction type;
forming a gate insulating layer at an edge of the bottom surface of the trench and on side walls of the trench; and
forming a gate on the gate insulating layer.

### Claim 12 (depends on 11)

The method as claimed in claim 11, wherein the vertically etching includes controlling an etching depth so that the bottom surface of the trench is in the drift region.

### Claim 13 (depends on 11)

The method as claimed in claim 11, wherein the doping the upper surface of the substrate and a bottom surface of the trench includes forming a first mask that covers the side walls of the trench so that only a central portion of the bottom surface of the trench is exposed and the edge of the bottom surface is covered, the first well region being on the upper surface of the substrate, the second well region being on the bottom surface of the trench exposed by the first mask.

### Claim 14 (depends on 13)

The method as claimed in claim 13, wherein the forming a first mask comprises:
depositing a mask material on the upper surface of the substrate and the side walls and the bottom surface of the trench; and
performing an anisotropic etching of the mask material such that the mask material remains only on the side walls of the trench.

### Claim 15 (depends on 13)

The method as claimed in claim 13, wherein the forming a first source region and a second source region comprises:
increasing a thickness of the first mask to form a second mask, the second mask overlapping the second well region; and
doping the first well region to the first conduction type to form the first source region and doping a portion of the second well region not overlapped by the second mask to the first conduction type to form the second source region such that the second well region entirely surrounds a lower surface and side surfaces of the second source region.

### Claim 16 (depends on 15)

The method as claimed in claim 15, wherein the vertically etching includes the lower region of the substrate being N+-doped and the drift region being N-doped, the doping the upper surface of the substrate and a bottom surface of the trench includes the first and second well regions being P-doped, and the forming a first source region and a second source region includes the first and second source regions being N+-doped.

### Claim 17 (depends on 15)

The method as claimed in claim 15, further comprising:
doping an edge of the first source region and a central portion of the second source region to the second conduction type to form a first ohmic contact layer and a second ohmic contact layer.

### Claim 18 (depends on 11)

The method as claimed in claim 11, wherein the forming a gate insulating layer and the forming a gate comprises:
forming a gate oxide layer on the upper surface of the substrate and on the side walls and the bottom surface of the trench to a uniform thickness;
depositing a gate material on the gate oxide layer; and
performing an anisotropic etching of the gate material such that the gate material remains only on the side walls of the trench.

### Claim 19 (depends on 18)

The method as claimed in claim 18, further comprising:
forming an interlayer insulating layer on the upper surface of the substrate and on the side walls and the bottom surface of the trench to cover the gate and the gate oxide layer;
partially removing the gate oxide layer and the interlayer insulating layer to expose parts of the first and second source regions; and
depositing a conductive material on the upper surface of the substrate and in the trench to form a source electrode.

### Claim 20 (depends on 11)

The method as claimed in claim 11, wherein
the forming a first source region and a second source region includes the first source region facing an upper portion of a side surface of the gate and the gate overlapping the second source region, and
the doping the upper surface of the substrate and a bottom surface of the trench includes the first well region being below an entirety of the first source region and the second well region entirely surrounding a bottom surface and side walls of the second source region, the gate overlapping a part of the second well region that surrounds the side walls of the second source region.