# US 2014/0197478 A1 · Power transistor device with super junction and manufacturing method thereof > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2014/0197478 A1 - Document ID: US20140197478A1 - Status: Published application - Kind: A1 - Application number: 14/221,258 - Filed: 2014-03-20 - Published: 2014-07-17 - Earliest claimed: 2011-11-29 - Assignees: Anpec Electronics Corporation - Applicants: Anpec Electronics Corporation - Inventors: Yung-Fa Lin; Shou-Yi Hsu; Meng-Wei Wu; Chia-Hao Chang - Web page: https://patentgrep.com/patent/US20140197478A1 ## CPC - H10D 30/66: Vertical DMOS [VDMOS] FETs - H10D 30/0291: {of vertical DMOS [VDMOS] FETs} - H10D 62/111: {Multiple RESURF structures, e.g. double RESURF or 3D-RESURF structures} - H10D 62/314: {having vertical doping variations (vertical IGFETs H10D30/63)} - H10D 62/393: {Body regions of DMOS transistors or IGBTs (cell layout of DMOS H10D62/127)} - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES ## Abstract The present invention provides a power transistor device with a super junction including a substrate, a first epitaxial layer, a second epitaxial layer, and a third epitaxial layer. The first epitaxial layer is disposed on the substrate, and has a plurality of trenches. The trenches are filled up with the second epitaxial layer, and a top surface of the second epitaxial layer is higher than a top surface of the first epitaxial layer. The second epitaxial layer has a plurality of through holes penetrating through the second epitaxial layer and disposed on the first epitaxial layer. The second epitaxial layer and the first epitaxial layer have different conductivity types. The through holes are filled up with the third epitaxial layer, and the third epitaxial layer is in contact with the first epitaxial layer. The third epitaxial layer and the first epitaxial layer have the same conductivity type. ## Claims ### Claim 1 A power transistor device with a super junction, comprising: a substrate having a first conductivity type; a first epitaxial layer disposed on the substrate and having a plurality of trenches; a second epitaxial layer filling up the trenches and a top surface of the second epitaxial layer is higher than a top surface of the first epitaxial layer, wherein the second epitaxial layer has a plurality of through holes penetrating through the second epitaxial layer and disposed on the first epitaxial layer, and the second epitaxial layer and the first epitaxial layer have different conductivity type; and a third epitaxial layer filling up the through holes and in contact with the first epitaxial layer, wherein the third epitaxial layer and the first epitaxial layer have the same conductivity type. ### Claim 2 (depends on 1) The power transistor device with a super junction according to claim 1, wherein the first epitaxial layer has a first conductivity type, and the second epitaxial layer has a second conductivity type different from the first conductivity type. ### Claim 3 (depends on 2) The power transistor device with a super junction according to claim 2, wherein the top surface of the second epitaxial layer is leveled with a top surface of the third epitaxial layer, and the power transistor device further comprises: a fourth epitaxial layer having the first conductivity type disposed on the second epitaxial layer and the third epitaxial layer, and wherein the fourth epitaxial layer is in contact with the second epitaxial layer and the third epitaxial layer; at least a gate structure disposed on the fourth epitaxial layer; at least a doped body region having the second conductivity type disposed in the fourth epitaxial layer on one side of the gate structure and partially overlapped with the gate structure, wherein the doped body region is in contact with the second epitaxial layer; and at least a doped source region having the first conductivity type disposed in the doped body region and partially overlapped by the gate structure. ### Claim 4 (depends on 2) The power transistor device with a super junction according to claim 2, wherein the third epitaxial layer extends to cover the second epitaxial layer and the power transistor device further comprises: at least a gate structure disposed on the third epitaxial layer; at least a doped body region having the second conductivity type disposed in the third epitaxial layer on one side of the gate structure and partially overlapped by the gate structure, wherein the doped body region is in contact with the second epitaxial layer; and at least a doped source region having the first conductivity type disposed in the doped body region and partially overlapped by the gate structure. ### Claim 5 (depends on 2) The power transistor device with a super junction according to claim 2, wherein a top surface of the third epitaxial layer is higher than a top surface of the second epitaxial layer, and the power transistor device further comprises at least a fifth epitaxial layer and at least a sixth epitaxial layer respectively disposed on the second epitaxial layer and the third epitaxial layer, and wherein the fifth epitaxial layer has the second conductivity type and the sixth epitaxial layer has the first conductivity type. ### Claim 6 (depends on 1) The power transistor device with a super junction according to claim 1, wherein the first epitaxial layer has a second conductivity type different from the first conductivity type, and the second epitaxial layer has a first conductivity type. ### Claim 7 (depends on 6) The power transistor device with a super junction according to claim 6, wherein the top surface of the second epitaxial layer is leveled with a top surface of the third epitaxial layer, and the power transistor device further comprises: a fourth epitaxial layer having the first conductivity type disposed on the second epitaxial layer and the third epitaxial layer, and wherein the fourth epitaxial layer is in contact with the second epitaxial layer and the third epitaxial layer; and at least a doped source region having the first conductivity type disposed in the fourth epitaxial layer and in contact with the third epitaxial layer. ### Claim 8 (depends on 6) The power transistor device with a super junction according to claim 6, wherein a top surface of the third epitaxial layer is higher than a top surface of the second epitaxial layer, and the power transistor device further comprises at least a fifth epitaxial layer having the first conductivity type disposed on the second epitaxial layer. ### Claim 9 (depends on 1) The power transistor device with a super junction according to claim 1, wherein the first epitaxial layer and the third epitaxial layer have different doping concentrations. ### Claim 10 (depends on 9) The power transistor device with a super junction according to claim 9, wherein the first epitaxial layer and the third epitaxial layer have different widths.