# US 2014/0197477 A1 · Semiconductor device

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- Number: US 2014/0197477 A1
- Document ID: US20140197477A1
- Status: Published application
- Kind: A1
- Application number: 14/156,574
- Filed: 2014-01-16
- Published: 2014-07-17
- Earliest claimed: 2013-01-16
- Assignees: Fuji Electric Co., Ltd.
- Applicants: Fuji Electric Co., Ltd.
- Inventors: Yasuhiko ONISHI
- Web page: https://patentgrep.com/patent/US20140197477A1

## CPC

- H10D 30/665: {having edge termination structures}
- H10D 62/109: {Reduced surface field [RESURF] PN junction structures}
- H10D 62/111: {Multiple RESURF structures, e.g. double RESURF or 3D-RESURF structures}
- H10D 30/0291: {of vertical DMOS [VDMOS] FETs}
- H10D 62/105: {by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE] (IGFETs having LDD or drain extension regions H10D30/601)}
- H10D 62/107: {Buried supplementary regions, e.g. buried guard rings (multi-RESURF H10D62/111)}
- H10D 62/112: {for preventing surface leakage due to surface inversion layers, e.g. by using channel stoppers}
- H10D 62/393: {Body regions of DMOS transistors or IGBTs (cell layout of DMOS H10D62/127)}
- H10D 64/111: {Field plates}
- H10D 64/252: {for vertical or pseudo-vertical devices}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A superjunction semiconductor device is disclosed in which the tradeoff relationship between on-resistance and breakdown voltage is improved greatly so that reverse recovery capability is improved. A drain drift portion substantially corresponds to a portion just under p-base regions serving as an active region and forms a first parallel pn structure in which a first n-type region and a first p-type region are joined to each other alternately and repeatedly. A drain drift portion is surrounded by edge termination region including a second parallel pn structure. Edge termination region is formed such that second n-type and p-type regions oriented consecutively to the first parallel pn structure of the drain drift portion are joined to each other alternately and repeatedly. N-buffer layer is provided between first and second parallel pn structures and n+ drain layer. P-buffer layer is provided selectively inside n-buffer layer in edge termination region.

## Claims

### Claim 1

A semiconductor device comprising:
an active region which is disposed on a first main surface side of a substrate to apply a current actively or passively;
a first conductivity-type low-resistivity layer which is disposed on a second main surface side of the substrate;
a vertical drift portion which is disposed between the active region and the low-resistivity layer so that a drift current flows into the vertical drift portion vertically in the ON state while the vertical drift portion is depleted in the OFF state, and which forms a first parallel pn structure in which a first vertical first conductivity-type region oriented in a thickness direction of the substrate and a first vertical second conductivity-type region oriented in the thickness direction of the substrate alternate repeatedly;
an edge termination region which is provided around the vertical drift portion and disposed between the first main surface and the low-resistivity layer, so that the edge termination region substantially serves as a region in which current does not flow in the ON state while the edge termination region is depleted in the OFF state;
a first conductivity-type layer which is provided between the first parallel pn structure and the low-resistivity layer so as to extend from the active region to the edge termination region and which has higher resistivity than the low-resistivity layer; and
a second conductivity-type layer which is provided selectively inside the first conductivity-type layer in the edge termination region.

### Claim 2 (depends on 1)

A semiconductor device according to claim 1, wherein the second conductivity-type layer is provided to extend from an interface between the active region and the edge termination region to an outer periphery of the edge termination region.

### Claim 3 (depends on 1)

A semiconductor device according to claim 1, wherein the edge termination region forms a second parallel pn structure in which a second vertical first conductivity-type region oriented in the thickness direction of the substrate and a second vertical second conductivity-type region oriented in the thickness direction of the substrate are joined to each other alternately and repeatedly, and the second conductivity-type layer is disposed at a distance from the second parallel pn structure.

### Claim 4 (depends on 3)

A semiconductor device according to claim 3, wherein a depth of the second parallel pn structure from the first main surface is shallower than a depth of the first parallel pn structure from the first main surface, and the second conductivity-type layer is separated from the second parallel pn structure by a first conductivity-type region provided between the second parallel pn structure and the first conductivity-type layer.

### Claim 5 (depends on 2)

A semiconductor device according to claim 2, wherein the edge termination region forms a second parallel pn structure in which a second vertical first conductivity-type region oriented in the thickness direction of the substrate and a second vertical second conductivity-type region oriented in the thickness direction of the substrate are joined to each other alternately and repeatedly, and the second conductivity-type layer is disposed at a distance from the second parallel pn structure.

### Claim 6 (depends on 5)

A semiconductor device according to claim 5, wherein a depth of the second parallel pn structure from the first main surface is shallower than a depth of the first parallel pn structure from the first main surface, and the second conductivity-type layer is separated from the second parallel pn structure by a first conductivity-type region provided between the second parallel pn structure and the first conductivity-type layer.