# US 2014/0197474 A1 · Semiconductor integrated circuit device and a method of manufacturing the same > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2014/0197474 A1 - Document ID: US20140197474A1 - Status: Published application - Kind: A1 - Application number: 14/217,748 - Filed: 2014-03-18 - Published: 2014-07-17 - Earliest claimed: 2002-04-18 - Assignees: Renesas Electronics Corporation - Applicants: Renesas Electronics Corporation - Inventors: Shoji SHUKURI - Web page: https://patentgrep.com/patent/US20140197474A1 ## CPC - H10B 43/30: characterised by the memory core region - B82Y 10/00: Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic - G11C 16/0466: {comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS] (G11C16/0483, G11C16/0491 take precedence)} - G11C 16/10: Programming or data input circuits - G11C 16/14: Circuits for erasing electrically, e.g. erase voltage switching circuits - G11C 16/26: Sensing or reading circuits; Data output circuits - H10B 41/30: characterised by the memory core region - H10B 41/40: characterised by the peripheral circuit region - H10B 41/49: comprising different types of peripheral transistor - H10B 43/35: with cell select transistors, e.g. NAND - H10B 43/40: characterised by the peripheral circuit region - H10B 69/00: Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices - H10D 30/0413: {of FETs having charge-trapping gate insulators, e.g. MNOS transistors} - H10D 30/6892: {having at least one additional gate other than the floating gate and the control gate, e.g. program gate, erase gate or select gate} - H10D 30/69: IGFETs having charge trapping gate insulators, e.g. MNOS transistors - H10D 30/696: {having at least one additional gate, e.g. program gate, erase gate or select gate} - H10D 64/035: {comprising conductor-insulator-conductor-insulator-semiconductor structures} - H10D 64/037: {comprising charge-trapping insulators} - H10D 64/516: {the thicknesses being non-uniform} - H10D 64/62: Electrodes ohmically coupled to a semiconductor - H10D 64/668: {the layer being a silicide, e.g. TiSi2} - H10D 64/685: {being perpendicular to the channel plane} - H10D 64/693: {the insulator comprising nitrogen, e.g. nitrides, oxynitrides or nitrogen-doped materials} - H10D 89/10: Integrated device layouts - H10W 20/20: Interconnections within wafers or substrates, e.g. through-silicon vias [TSV] - G11C 16/34: Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention - H10D 30/0411: {of FETs having floating gates} - H10B: ELECTRONIC MEMORY DEVICES - B82Y: SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES - G11C: STATIC STORES (semiconductor memory devices H10B) - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract Semiconductor device including a memory cell featuring a first gate insulating film over a semiconductor substrate, a control gate electrode over the first gate insulating film, a second gate insulating film over the substrate and a side wall of the control gate electrode, a memory gate electrode over the second gate insulating film arranged adjacent with the control gate electrode through the second gate insulating film, first and second semiconductor regions in the substrate positioned on a control gate electrode side and a memory gate side, respectively, the second gate insulating film featuring a first film over the substrate, a charge storage film over the first film and a third film over the second film, the first film having a first portion between the substrate and memory gate electrode and a thickness greater than that of a second portion between the control gate electrode and the memory gate electrode. ## Claims ### Claim 1 A semiconductor device having a memory cell; the memory cell comprising: a first gate insulating film formed over a semiconductor substrate, a control gate electrode formed over the first gate insulating film, a second gate insulating film formed over the semiconductor substrate and over a side wall of the control gate electrode, a memory gate electrode formed over the second gate insulating film and arranged adjacent with the control gate electrode through the second gate insulating film, a first semiconductor region formed in the semiconductor substrate and positioned on a control gate electrode side, and a second semiconductor region formed in the semiconductor substrate and positioned on a memory gate electrode side, wherein the second gate insulating film includes a first insulating film, a second insulating film, and a third insulating film, wherein the first insulating film is formed over the semiconductor substrate and over a side wall of the control gate electrode, wherein the second insulating film is formed over the first insulating film and contacts the first insulating film between the memory gate electrode and the semiconductor substrate and between the control gate electrode and the memory gate electrode, wherein the third insulating film is formed over the second insulating film, wherein the second insulating film includes a charge storage film, and wherein an contacting face of the first insulating film and the second insulating film has a corner whose interior angle takes a form of an acute angle in a cross-section view. ### Claim 2 (depends on 1) A semiconductor device according to the claim 1, wherein the first insulating film includes a first portion and a second portion, wherein the first portion is located between the memory gate electrode and the semiconductor substrate, and the second portion is located between the control gate electrode and the memory gate electrode, and wherein a thickness of a lower portion of the second portion is smaller than a thickness of a middle portion of the second portion. ### Claim 3 (depends on 2) A semiconductor device according to the claim 2, wherein a thickness of the second portion is greater than a thickness of the first portion. ### Claim 4 (depends on 1) A semiconductor device according to the claim 1, wherein the first insulating film includes a first portion and a second portion, wherein the first portion is located between the memory gate electrode and the semiconductor substrate, and the second portion is located between the control gate electrode and the memory gate electrode, and wherein a thickness of the second portion is greater than a thickness of the first portion. ### Claim 5 (depends on 1) A semiconductor device according to the claim 1, wherein the first and third insulating film include a silicon oxide film, and wherein the second insulating film includes a silicon nitride film. ### Claim 6 (depends on 1) A semiconductor device according to the claim 1, wherein the memory gate electrode is in a form of a side wall. ### Claim 7 (depends on 1) A semiconductor device according to the claim 1, wherein charge storage film includes a silicon nitride film. ### Claim 8 A semiconductor device having a memory cell; the memory cell comprising: a first gate insulating film formed over a semiconductor substrate, a control gate electrode formed over the first gate insulating film, a second gate insulating film formed over the semiconductor substrate and over a side wall of the control gate electrode, a memory gate electrode formed over the second gate insulating film and arranged adjacent with the control gate electrode through the second gate insulating film, a first semiconductor region formed in the semiconductor substrate and positioned on a control gate electrode side, and a second semiconductor region formed in the semiconductor substrate and positioned on a memory gate electrode side, wherein the second gate insulating film includes a first insulating film, a second insulating film, and a third insulating film, wherein the first insulating film is formed over the semiconductor substrate and over a side wall of the control gate electrode, wherein the second insulating film is formed over the first insulating film and contacts the first insulating film between the memory gate electrode and the semiconductor substrate and between the control gate electrode and the memory gate electrode, wherein the third insulating film is formed over the second insulating film, wherein the second insulating film includes a charge storage film, wherein a contacting face of the first insulating film and the second insulating film includes a first portion and a second portion, wherein the first portion is located between the memory gate electrode and the semiconductor substrate, and the second portion is located between the control gate electrode and the memory gate electrode, and wherein the first portion and the second portion intersect so as to take a form of an interior acute angle in a cross-section view. ### Claim 9 (depends on 8) A semiconductor device according to the claim 8, wherein the first insulating film includes a third portion and a fourth portion, wherein the third portion is located between the memory gate electrode and the semiconductor substrate, and the fourth portion is located between the control gate electrode and the memory gate electrode, and wherein a thickness of a lower portion of the fourth portion is smaller than a thickness of a middle portion of the fourth portion. ### Claim 10 (depends on 9) A semiconductor device according to the claim 9, wherein a thickness of the fourth portion is greater than a thickness of the third portion. ### Claim 11 (depends on 8) A semiconductor device according to the claim 8, wherein the first insulating film includes a third portion and a fourth portion, wherein the third portion is located between the memory gate electrode and the semiconductor substrate, and the fourth portion is located between the control gate electrode and the memory gate electrode, and wherein a thickness of the fourth portion is greater than a thickness of the third portion. ### Claim 12 (depends on 8) A semiconductor device according to the claim 8, wherein the first and third insulating film include a silicon oxide film, and wherein the second insulating film includes a silicon nitride film. ### Claim 13 (depends on 8) A semiconductor device according to the claim 8, wherein the memory gate electrode is in a form of a side wall. ### Claim 14 (depends on 8) A semiconductor device according to the claim 8, wherein charge storage film includes a silicon nitride film.