# US 2014/0197473 A1 · Nonvolatile semiconductor storage device and method of manufacturing the same > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2014/0197473 A1 - Document ID: US20140197473A1 - Status: Published application - Kind: A1 - Application number: 14/010,662 - Filed: 2013-08-27 - Published: 2014-07-17 - Earliest claimed: 2013-01-17 - Assignees: Kabushiki Kaisha Toshiba - Applicants: Kabushiki Kaisha Toshiba - Inventors: Kenichi FUJII; Akira YOTSUMOTO; Takaya YAMANAKA; Fumie KIKUSHIMA - Web page: https://patentgrep.com/patent/US20140197473A1 ## CPC - H10W 10/014: {using trench refilling with dielectric materials, e.g. shallow trench isolations} - G11C 16/00: Erasable programmable read-only memories (G11C14/00 takes precedence) - G11C 16/0408: {comprising cells containing floating gate transistors (G11C16/0483, G11C16/0491 take precedence)} - H10B 41/35: with a cell select transistor, e.g. NAND - H10D 30/0411: {of FETs having floating gates} - H10W 10/17: formed using trench refilling with dielectric materials, e.g. shallow trench isolations - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 - G11C: STATIC STORES (semiconductor memory devices H10B) - H10B: ELECTRONIC MEMORY DEVICES - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES ## Abstract A nonvolatile semiconductor storage device includes a substrate; an isolation film extending in a first direction and dividing the substrate into element regions; a cell string including memory cells in the element regions; a cell unit including the cell string and a select transistor on first directional ends of the cell string; diffusion layers formed in a portion of the element region first directionally beside the select gate electrode, the diffusion layers being adjacent to one another in a second direction intersecting with the first direction; and contacts extending through an interlayer insulating film and contacting the diffusion layers. An upper surface of the isolation film located between the diffusion layers is lower than an upper surface of the substrate. A laminate of silicon oxide film and a silicon nitride film are located above the upper surface of the isolation film and below the upper surface of the substrate. ## Claims ### Claim 1 A nonvolatile semiconductor storage device, comprising: a semiconductor substrate; an element isolation film that extends in a first direction and that divides the semiconductor substrate into a plurality of element regions; a cell string including a plurality of memory cells disposed along the first direction in the element regions; a cell unit including the cell string and a select transistor located on each of ends of the cell string in the first direction; a plurality of diffusion layers each formed in a portion of the element region located beside the select gate electrode in the first direction, each of the diffusion layers being arranged to be adjacent to one another in a second direction intersecting with the first direction; an interlayer insulating film formed above the plurality of diffusion layers; and a plurality of contacts extending through the interlayer insulating film and contacting the diffusion layers respectively; wherein an upper surface the element isolation film located between the diffusion layers is lower than an upper surface of the semiconductor substrate; and wherein a silicon oxide film and a silicon nitride film disposed above the silicon oxide film are provided above the upper surface of the element isolation film and below the upper surface of the semiconductor substrate. ### Claim 2 (depends on 1) The device according to claim 1, wherein a bottom surface of each of the diffusion layers is lower than the upper surface of the element isolation film. ### Claim 3 (depends on 1) The device according to claim 1, wherein the silicon oxide film forms a recess between the adjacent diffusion layers, and wherein the silicon nitride film includes a first silicon nitride film formed along an inner side of the recess and a second silicon nitride film formed above the first silicon nitride film. ### Claim 4 (depends on 3) The device according to claim 3, wherein the second silicon nitride film is thicker than the first silicon nitride film. ### Claim 5 (depends on 1) The device according to claim 1, wherein the semiconductor substrate is a silicon substrate, and wherein each of the diffusion layers contains arsenic. ### Claim 6 (depends on 3) The device according to claim 3, wherein the first silicon nitride film contains carbon. ### Claim 7 (depends on 3) The device according to claim 3, wherein the second silicon nitride film contains carbon. ### Claim 8 (depends on 1) The device according to claim 1, wherein the contact includes a bottom surface which is higher than the lowermost surface of the first silicon nitride film. ### Claim 9 A method of manufacturing a nonvolatile semiconductor device comprising: dividing a semiconductor substrate into a plurality of element regions by defining a plurality of trenches extending in a first direction into the semiconductor substrate so as to be aligned in a second direction intersecting with the first direction and filling the trenches with an element isolation film; exposing an upper surface of the element regions by lowering an upper surface of the element isolation film so as to be lower than an upper surface of the semiconductor substrate; forming a silicon oxide film along an upper surface and an upper sidewall of the element regions and along the upper surface of the element isolation film so as to form recesses on an upper side thereof; filling the recesses with the first silicon nitride film; forming a plurality of diffusion layers in a surface layer of the element regions after filling the recesses with the first silicon nitride film; forming a second silicon nitride film thicker than the first silicon nitride film above the first silicon nitride film; forming an interlayer insulating film above the second silicon nitride film; forming a plurality of holes through the interlayer insulating film using the second silicon nitride film as a stopper; extending the holes to expose each of the diffusion layers; and filling the holes with a contact. ### Claim 10 (depends on 9) The method according to claim 9, wherein doping impurities forms the diffusion layers such that a bottom surface of each of the diffusion layers is lower than the upper surface of the element isolation film. ### Claim 11 (depends on 9) The method according to claim 9, wherein the semiconductor substrate is a silicon substrate, the impurities comprise arsenic. ### Claim 12 (depends on 9) The method according to claim 9, wherein the first silicon nitride film contains carbon. ### Claim 13 (depends on 9) The method according to claim 9, wherein the second silicon nitride film contains carbon. ### Claim 14 (depends on 9) The method according to claim 9, wherein forming the diffusion layers precedes forming the second nitride film and wherein forming the diffusion layers includes doping impurities into the surface layer of the plurality of element regions. ### Claim 15 (depends on 14) The method according to claim 14, wherein forming the diffusion layers further includes activating the doped impurities.