# US 2014/0197472 A1 · Non-volatile memory structure and manufacturing method thereof

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- Number: US 2014/0197472 A1
- Document ID: US20140197472A1
- Status: Published application
- Kind: A1
- Application number: 13/741,399
- Filed: 2013-01-15
- Published: 2014-07-17
- Earliest claimed: 2013-01-15
- Assignees: United Microelectronics Corp.
- Applicants: United Microelectronics Corp.
- Inventors: Wen-Chung Chang; Shen-De Wang; Ya-Huei Huang; Feng-Ji Tsai; Chien-Hung Chen
- Web page: https://patentgrep.com/patent/US20140197472A1

## CPC

- H10D 30/0413: {of FETs having charge-trapping gate insulators, e.g. MNOS transistors}
- H10B 43/40: characterised by the peripheral circuit region
- H10B 43/50: characterised by the boundary region between the core and peripheral circuit regions
- H10D 30/69: IGFETs having charge trapping gate insulators, e.g. MNOS transistors
- H10D 30/694: {characterised by the shapes, relative sizes or dispositions of the gate electrodes}
- H10D 64/037: {comprising charge-trapping insulators}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10B: ELECTRONIC MEMORY DEVICES

## Abstract

A method for manufacturing a non-volatile memory structure includes providing a substrate having a memory region and a logic region defined thereon, masking the logic region while forming at least a first gate in the memory region, forming an oxide-nitride-oxide (ONO) structure under the first gate, forming an oxide structure covering the ONO structure on the substrate, masking the memory region while forming a second gate in the logic region, and forming a first spacer on sidewalls of the first gate and a second spacer on sidewalls of the second gate simultaneously.

## Claims

### Claim 1

A method for manufacturing a non-volatile memory structure, comprising:
providing a substrate having a memory region and a logic region defined thereon, and a dielectric layer and a conductive layer being sequentially formed on the substrate;
masking the logic region while etching the dielectric layer and the conductive layer in the memory region to form at least a first gate in the memory region;
forming an oxide-nitride-oxide (ONO) structure under the first gate and near sidewalls of the first gate;
forming an oxide structure covering the ONO structure on the substrate;
masking the memory region while etching the conductive layer and the dielectric layer in the logic region to form at least a second gate in the logic region; and
forming a first spacer on sidewalls of the first gate and a second spacer on sidewalls of the second gate simultaneously.

### Claim 2 (depends on 1)

The method for manufacturing the non-volatile memory structure according to claim 1, wherein the ONO structure is formed by steps comprising:
forming a cavity in the dielectric layer of the first gate;
forming a first oxide layer on the substrate, the first oxide layer covering a bottom of the first gate and a portion of the substrate;
forming a first nitride layer filling up the cavity on the substrate; and
removing a portion of the first nitride layer to form the ONO structure.

### Claim 3 (depends on 1)

The method for manufacturing the non-volatile memory structure according to claim 1, wherein the oxide structure is formed by steps comprising:
forming a second oxide layer on the substrate; and
removing portions of the second oxide layer to form the oxide structure, and the oxide structure covering the ONO structure.

### Claim 4 (depends on 3)

The method for manufacturing the non-volatile memory structure according to claim 3, wherein a thickness of the second oxide layer is between 100 angstroms (Å) and 1000Å.

### Claim 5 (depends on 3)

The method for manufacturing the non-volatile memory structure according to claim 3, wherein a thickness of the oxide structure is between 50Å and 600Å.

### Claim 6 (depends on 1)

The method for manufacturing the non-volatile memory structure according to claim 1, further comprising forming first lightly-doped drains (LDDs) in the substrate at two respective sides of the first gate before forming the second gate in the logic region.

### Claim 7 (depends on 1)

The method for manufacturing the non-volatile memory structure according to claim 1, wherein the first spacer and the second spacer are formed by steps comprising:
sequentially forming a third oxide layer and a second nitride layer on the substrate; and
removing portions of the second nitride layer and the third oxide layer to form the first spacer and the second spacer.

### Claim 8 (depends on 1)

The method for manufacturing the non-volatile memory structure according to claim 1, further comprising forming second LDDs in the substrate at two respective sides of the second gate before forming the first spacer and the second spacer.

### Claim 9 (depends on 1)

The method for manufacturing the non-volatile memory structure according to claim 1, further comprising forming a first source/drain in the substrate at two respective sides of the first gate and forming a second source/drain in the substrate at two respective sides of the second gate.

### Claim 10

A non-volatile memory structure comprising:
a substrate having a memory region and a logic region defined thereon;
a first gate forming in the memory region and a second gate formed in the logic region;
an ONO structure disposed under the first gate;
an oxide structure disposed on sidewalls of the first gate; and
a first spacer disposed on the sidewalls of the first gate and a second spacer disposed on sidewalls of the second gate.

### Claim 11 (depends on 10)

The non-volatile memory structure according to claim 10, wherein the first gate and the second gate respectively comprise a conductive layer and a dielectric layer.

### Claim 12 (depends on 11)

The non-volatile memory structure according to claim 11, wherein the ONO structure further comprises:
first oxide layers formed on a bottom of the conductive layer and on the substrate under the first gate; and
a first nitride layer sandwiched between the first oxide layers and covering the sidewalls of the first gate.

### Claim 13 (depends on 10)

The non-volatile memory structure according to claim 10, wherein a thickness of the oxide structure is between 50Å and 600Å.

### Claim 14 (depends on 10)

The non-volatile memory structure according to claim 10, wherein the first spacer and the second spacer respectively comprise at least a second oxide layer.

### Claim 15 (depends on 14)

The non-volatile memory structure according to claim 14, wherein the oxide structure is sandwiched between the ONO structure and the second oxide layer.

### Claim 16 (depends on 14)

The non-volatile memory structure according to claim 14, wherein the second spacer further comprises a second nitride layer formed on the second oxide layer.

### Claim 17 (depends on 10)

The non-volatile memory structure according to claim 10, further comprising first LDDs formed in the substrate at two respective sides of the first gate and second LDDs formed in the substrate at two respective sides of the second gate.

### Claim 18 (depends on 10)

The non-volatile memory structure according to claim 10, further comprising a first source/drain in the substrate at two respective sides of the first gate and a second source/drain formed in the substrate at two respective sides of the second gate.