# US 2014/0197471 A1 · Non-volatile memory devices having reduced susceptibility to leakage of stored charges and methods of forming same

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- Number: US 2014/0197471 A1
- Document ID: US20140197471A1
- Status: Published application
- Kind: A1
- Application number: 14/218,293
- Filed: 2014-03-18
- Published: 2014-07-17
- Earliest claimed: 2009-09-30
- Assignees: Samsung Electronics Co., Ltd.
- Applicants: Samsung Electronics Co., Ltd.
- Inventors: Albert Fayrushin; Kwang Soo Seol; Jaeduk Lee
- Web page: https://patentgrep.com/patent/US20140197471A1

## CPC

- H10D 30/694: {characterised by the shapes, relative sizes or dispositions of the gate electrodes}
- H10B 41/30: characterised by the memory core region
- H10D 30/0411: {of FETs having floating gates}
- H10D 30/681: {having only two programming levels (Floating gate IGFETs programmable by two single electrons H10D30/688)}
- H10D 30/683: {programmed by tunnelling of carriers, e.g. Fowler-Nordheim tunnelling}
- H10D 30/6894: {having one gate at least partly in a trench}
- H10D 30/69: IGFETs having charge trapping gate insulators, e.g. MNOS transistors
- H10B 43/30: characterised by the memory core region
- H10D 30/0413: {of FETs having charge-trapping gate insulators, e.g. MNOS transistors}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10B: ELECTRONIC MEMORY DEVICES

## Abstract

Provided is a semiconductor device. The semiconductor device includes a substrate, a tunnel insulating layer, a charge storage pattern, a blocking layer, a gate electrode. The tunnel insulating layer is disposed over the substrate. The charge storage pattern is disposed over the tunnel insulating layer. The charge storage pattern has an upper surface, a sidewall, and an edge portion between the upper surface and the sidewall. The blocking layer includes an insulating pattern covering the edge portion of the charge storage pattern, and a gate dielectric layer covering the upper surface, the sidewall, and the edge portion of the charge storage pattern. The gate electrode is disposed over the blocking layer, the gate electrode covering the upper surface, the sidewall, and the edge portion of the charge storage pattern.

## Claims

### Claim at position 1

-8. (canceled)

### Claim 9

A semiconductor device comprising:
a device isolation layer defining an active region in a substrate;
a tunnel insulating layer on the active region;
a charge storage pattern on the tunnel insulating layer, wherein the charge storage pattern comprises an upper surface, a sidewall, and an edge portion between the upper surface and the sidewall;
a blocking layer on the charge storage pattern, wherein the blocking layer comprises a gate dielectric layer covering the upper surface, the sidewall, and the edge portion of the charge storage pattern and a spacer covering the edge portion of the charge storage pattern and exposing a portion of the gate dielectric layer covering the upper surface of the charge storage pattern; and
a gate electrode on the blocking layer,
wherein a thickness of a first portion of the blocking layer covering the edge portion of the charge storage pattern is greater than a thickness of a second portion of the blocking layer covering the sidewall of the charge storage pattern, and the spacer is between the gate dielectric layer and the gate electrode.

### Claim 10 (depends on 9)

The semiconductor device of claim 9, wherein:
the gate electrode comprises a lower electrode and an upper electrode; and
the spacer directly contacts an upper surface of the lower electrode.

### Claim 11 (depends on 10)

The semiconductor device of claim 10, wherein the lower electrode directly contacts a portion of the gate dielectric layer covering the sidewall of the charge storage pattern.

### Claim 12 (depends on 10)

The semiconductor device of claim 10, wherein the lower gate electrode and the upper gate electrode define a discontinuous interface therebetween.

### Claim 13 (depends on 9)

The semiconductor device of claim 9, wherein a bottom surface of the charge storage pattern directly contacts the tunnel insulating layer and the charge storage pattern has a tapered profile from the bottom surface to the upper surface of the charge storage pattern.

### Claim 14 (depends on 9)

The semiconductor device of claim 9, wherein:
the gate dielectric layer comprises a first material; and
the spacer comprises a second material different from the first material and covers the gate dielectric layer.

### Claim 15 (depends on 9)

The semiconductor device of claim 9, wherein the charge storage pattern has a slanted straight sidewall.

### Claim 16 (depends on 9)

The semiconductor device of claim 9, wherein:
the blocking layer further comprises an insulating pattern between the charge storage pattern and the gate dielectric layer; and
the insulating pattern covers the edge portion of the charge storage pattern.

### Claim 17 (depends on 16)

The semiconductor device of claim 16, wherein:
the insulating pattern is spaced apart from the device isolation layer; and
the gate dielectric layer directly contacts the sidewall of the charge storage pattern.

### Claim 18 (depends on 17)

The semiconductor device of claim 17, wherein the gate dielectric layer directly contacts an upper surface of the device isolation layer.

### Claim 19 (depends on 16)

The semiconductor device of claim 16, wherein the insulating pattern and the gate dielectric layer are provided through different processes.

### Claim 20 (depends on 16)

The semiconductor device of claim 16, wherein the insulating pattern and the gate dielectric layer are provided with a discontinuous surface therebetween and are divided by the discontinuous surface.

### Claim 21 (depends on 16)

The semiconductor device of claim 16, wherein:
the edge portion of the charge storage pattern has a curved surface;
the insulating pattern is extended from the edge portion to the upper surface of the charge storage pattern; and
a thickness of a third portion of the blocking layer covering the upper surface of the charge storage pattern is greater than the thickness of the second portion of the blocking layer covering the sidewall of the charge storage pattern.

### Claim 22 (depends on 21)

The semiconductor device of claim 21, wherein the gate dielectric layer covers the insulating pattern.

### Claim 23 (depends on 16)

The semiconductor device of claim 16, wherein the insulating pattern comprises a first material and the gate dielectric layer comprises a second material different from the first material.

### Claim 24 (depends on 23)

The semiconductor device of claim 23, wherein the first material is silicon oxide and the second material is silicon nitride, silicon oxynitride or a high dielectric material.

### Claim 25 (depends on 23)

The semiconductor device of claim 23, wherein:
an upper surface of the insulating pattern is higher than the upper surface of the charge storage pattern; and
a bottom surface of the insulating pattern is between a bottom surface of the charge storage pattern and the upper surface of the charge storage pattern.

### Claim 26 (depends on 23)

The semiconductor device of claim 23, wherein a portion of the gate dielectric layer directly contacting the insulating pattern comprises the second material.

### Claim 27 (depends on 16)

The semiconductor device of claim 16, wherein the insulating pattern directly contacts the charge storage pattern.

### Claim 28 (depends on 16)

The semiconductor device of claim 16, wherein the insulating pattern covers an entirety of the upper surface of the charge storage pattern.