# US 2014/0197469 A1 · Three-dimensional semiconductor devices with current path selection structure and methods of operating the same

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- Number: US 2014/0197469 A1
- Document ID: US20140197469A1
- Status: Published application
- Kind: A1
- Application number: 14/150,452
- Filed: 2014-01-08
- Published: 2014-07-17
- Earliest claimed: 2013-01-11
- Assignees: Samsung Electronics Co., Ltd.
- Inventors: Jaeduk Lee; Youngwoo Park; Jintaek Park; Dohyun Lee; Kohji Kanamori
- Web page: https://patentgrep.com/patent/US20140197469A1

## CPC

- G11C 16/10: Programming or data input circuits
- G11C 16/14: Circuits for erasing electrically, e.g. erase voltage switching circuits
- H10B 41/27: the channels comprising vertical portions, e.g. U-shaped channels
- H10B 41/35: with a cell select transistor, e.g. NAND
- G11C: STATIC STORES (semiconductor memory devices H10B)
- H10B: ELECTRONIC MEMORY DEVICES

## Abstract

Provided are three-dimensional semiconductor devices and methods of operating the same. The three-dimensional semiconductor devices may include active patterns arranged on a substrate to have a multi-layered and multi-column structure and drain patterns connected to respective columns of the active patterns. The methods may include a layer-selection step connecting a selected one of layers of the active patterns selectively to the drain patterns. For example, the layer-selection step may be performed in such a way that widths of depletion regions to be formed in end-portions of the active patterns are differently controlled depending on to a height from the substrate.

## Claims

### Claim 1

A three-dimensional semiconductor memory device, comprising:
a common source structure, a string selection structure, and a memory structure on a substrate, the memory structure interposed between the common source structure and the string selection structure,
wherein the memory structure comprises a plurality of sequentially stacked active patterns elongated parallel to a top surface of the substrate, gate patterns extending perpendicular to the top surface of the substrate, and memory elements interposed between the active patterns and the gate patterns, and
wherein the string selection structure comprises:
drain patterns elongated perpendicular to the top surface of the substrate to connect end-portions of the active patterns to each other; and
layer-selection patterns sequentially stacked to control an energy band structure of respective ones of the end-portions of the sequentially stacked active patterns located at a same level.

### Claim 2 (depends on 1)

The device of claim 1, wherein the drain patterns comprise a semiconductor material in direct contact with the active patterns and having the same conductivity type as the active patterns.

### Claim 3 (depends on 2)

The device of claim 2, wherein the drain patterns comprise an n- or p-type highly-doped semiconductor material, and
the active patterns comprise a lightly-doped semiconductor material having the same conductivity type as the drain patterns.

### Claim 4 (depends on 1)

The device of claim 1, wherein the layer-selection patterns comprise a semiconductor material in direct contact with the active patterns and having a different conductivity type from the active patterns.

### Claim 5 (depends on 4)

The device of claim 4, wherein the drain patterns comprise a semiconductor material being in direct contact with the active patterns having a different conductivity type from the active patterns, and
the drain patterns have an impurity concentration higher than the active patterns.

### Claim 6 (depends on 1)

The device of claim 1, wherein the string selection structure further comprises a string selection insulating layer electrically insulating the active patterns from the layer-selection patterns.

### Claim 7 (depends on 6)

The device of claim 6, wherein each of the layer-selection patterns and end-portions of the active patterns located adjacent thereto are configured as metal-oxide-semiconductor (MOS) capacitors.

### Claim 8 (depends on 1)

The device of claim 1, wherein the active patterns are arranged in horizontal and vertical directions to have a multi-layered and multi-column structure, and
a respective one of the drain patterns is provided between a corresponding pair of columns of the active patterns.

### Claim 9 (depends on 8)

The device of claim 8, wherein a respective one of the drain patterns is connected in common to a plurality of the active patterns that constitute a corresponding one of the columns and are arranged at different levels from each other.

### Claim 10 (depends on 8)

The device of claim 8, wherein a respective one of the layer-selection patterns is connected in common to a plurality of the active patterns that constitute a corresponding one of the layers and are arranged at different columns from each other.

### Claim at position 11

-14. (canceled)

### Claim 15

A three-dimensional semiconductor memory device, comprising:
a first layer comprising first and second active patterns;
a second layer comprising third and fourth active patterns;
a first drain pattern connected to the first and third active patterns;
a second drain pattern connected to the second and fourth active patterns;
a first layer-selection pattern configured to control depths of depletion regions in the first and second active patterns; and
a second layer-selection pattern configured to control depths of depletion regions in the third and fourth active patterns.

### Claim 16 (depends on 15)

The device of claim 15, wherein the first drain patterns comprise a semiconductor material in direct contact with the first and third active patterns and having a same conductivity type as the first and third active patterns, and
the second drain patterns comprises a semiconductor material in direct contact with the second and fourth active patterns and having a same conductivity type as the second and fourth active patterns.

### Claim 17 (depends on 15)

The device of claim 15, wherein the first and second drain patterns comprise an n- or p-type semiconductor material, and
the first to fourth active patterns comprise a semiconductor material having the same conductivity type as the first and second drain patterns.

### Claim 18 (depends on 15)

The device of claim 15, wherein the first layer-selection pattern comprises a semiconductor material in direct contact with the first and second active patterns and having a different conductivity type from the first and second active patterns.

### Claim 19 (depends on 18)

The device of claim 18, wherein the first drain patterns comprise a semiconductor material in direct contact with the first and third active patterns and having a same conductivity type as the first and third active patterns,
the second drain patterns comprise a semiconductor material in direct contact with the second and fourth active patterns and having a same conductivity type as the second and fourth active patterns, and
each of the first and second drain patterns have an impurity concentration higher than the first to fourth active patterns.

### Claim 20

(canceled)

### Claim 21

A three-dimensional semiconductor memory device, comprising:
an active structure including active patterns that are arranged in horizontal and vertical directions on a substrate;
a first common source electrode connected in common to end-portions of the active patterns; and
a second common source electrode connected in common to the end-portions of the active patterns,
wherein the first and second common source electrodes comprise semiconductor materials having different conductivity types from each other.

### Claim at position 19

-23. (canceled)

### Claim 24 (depends on 21)

The device of claim 21, wherein each of the active patterns comprises:
an outer sidewall defining an outer boundary of the active structure; and
inner sidewalls positioned in the active structure to face others of the active patterns adjacent thereto,
wherein the first common source electrode is connected to the inner sidewalls of the active patterns, and
the second common source electrode is connected to the outer sidewalls of the active patterns.

### Claim 25 (depends on 21)

The device of claim 21, wherein the first common source electrode comprises a plurality of source plugs elongated along the vertical direction and interposed between the active patterns, and
the second common source electrode is connected in common to the active patterns arranged along the horizontal and the vertical directions.

### Claim at position 22

-27. (canceled)

### Claim 28 (depends on 25)

The device of claim 25, wherein each of the source plugs comprises a pair of junction portions covering two columns, respectively, of the active patterns arranged adjacent thereto and a connecting portion facing the second common source electrode and connecting the junction portions, thereby having ‘U’-shaped horizontal section.

### Claim at position 24

-31. (canceled)

### Claim 32 (depends on 21)

The device of claim 21, wherein the second common source electrode comprises:
a plate electrode disposed at a side of the active structure; and
at least one contact electrode interposed between the plate electrode and the active structure,
wherein the plate electrode comprises a material, whose resistivity is lower than the at least one contact electrode.

### Claim 33 (depends on 32)

The device of claim 32, wherein the at least one contact electrode comprises a plurality of contact electrodes that are one-dimensional or two-dimensionally arranged on a sidewall of the plate electrode.

### Claim at position 27

-37. (canceled)

### Claim 38

A three-dimensional semiconductor memory device, comprising:
a common source structure, a string selection structure, and a memory structure on a substrate, the memory structure interposed between the common source structure and the string selection structure,
wherein the memory structure comprises a plurality of sequentially stacked active patterns elongated parallel to a top surface of the substrate, gate patterns extending perpendicular to the top surface of the substrate, and memory elements interposed between the active patterns and the gate patterns, and
wherein the string selection structure is configured to select a plurality of the memory elements at a given level relative to the top surface of the substrate, while simultaneously refraining from selecting other memory elements that overlie or underlie the plurality of memory elements at the given level.

### Claim 39 (depends on 39)

The device of claim 39 wherein the string selection structure comprises:
drain patterns elongated perpendicular to the top surface of the substrate to connect end portions of the active patterns to each other; and
layer-selection patterns sequentially stacked on the substrate.

### Claim 40 (depends on 39)

The device of claim 39, wherein the active patterns are arranged in horizontal and vertical directions to have a multi-layered and multi-column structure, and
each of the drain patterns is provided between a corresponding pair of columns of the active patterns.

### Claim 41 (depends on 40)

The device of claim 40, wherein each of the drain patterns is connected in common to a plurality of the active patterns that constitute a corresponding one of the columns and are arranged at different levels from each other.

### Claim 42 (depends on 39)

The device of claim 39 wherein the string selection structure is further configured to connect a selected one of the active patterns to the drain patterns, such that the widths of depletion regions formed in end-portions of the active patterns are differently controlled depending on a distance from the substrate.