# US 2014/0197468 A1 · Methods of forming semiconductor device with self-aligned contact elements and the resulting device

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- Number: US 2014/0197468 A1
- Document ID: US20140197468A1
- Status: Published application
- Kind: A1
- Application number: 13/743,454
- Filed: 2013-01-17
- Published: 2014-07-17
- Earliest claimed: 2013-01-17
- Assignees: Globalfoundries Inc.
- Applicants: Globalfoundries Inc.
- Inventors: Ruilong Xie; Xiuyu Cai
- Web page: https://patentgrep.com/patent/US20140197468A1

## CPC

- H10D 64/259: {Source or drain electrodes being self-aligned with the gate electrode and having bottom surfaces higher than the interface between the channel and the gate dielectric}
- H10D 30/0215: {using self-aligned selective metal deposition simultaneously on gate electrodes and the source regions or drain regions}
- H10D 30/024: {of fin field-effect transistors [FinFET]}
- H10D 30/60: Insulated-gate field-effect transistors [IGFET] (H10D30/40 takes precedence)
- H10D 30/6211: {having fin-shaped semiconductor bodies integral with the bulk semiconductor substrates}
- H10D 30/6219: {characterised by the source or drain electrodes}
- H10D 64/015: {removing at least parts of gate spacers, e.g. disposable spacers}
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D 64/021: {using multiple gate spacer layers, e.g. bilayered sidewall spacers}
- H10W 20/069: {by forming self-aligned vias or self-aligned contact plugs}
- H10W 20/077: {on sidewalls or on top surfaces of conductors (H10W20/076 takes precedence)}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

One method disclosed includes forming a final gate structure in a gate cavity that is laterally defined by sidewall spacers, removing a portion of the sidewall spacers to define recessed sidewall spacers, removing a portion of the final gate structure to define a recessed final gate structure and forming an etch stop on the recessed sidewall spacers and the recessed final gate structure. A transistor device disclosed herein includes a final gate structure that has an upper surface positioned at a first height level above a surface of a substrate, sidewall spacers positioned adjacent the final gate structure, the sidewall spacers having an upper surface that is positioned at a second, greater height level above the substrate, an etch stop layer formed on the upper surfaces of the sidewall spacers and the final gate structure, and a conductive contact that is conductively coupled to a contact region of the transistor.

## Claims

### Claim 1

A method of forming a transistor, comprising:
forming a final gate structure in a gate cavity that is laterally defined by sidewall spacers;
removing a portion of said sidewall spacers to define recessed sidewall spacers;
removing a portion of said final gate structure to define a recessed final gate structure; and
forming an etch stop layer on at least said recessed sidewall spacers and said recessed final gate structure.

### Claim 2 (depends on 1)

The method of claim 1, wherein an upper surface of said recessed sidewall spacers define, in part, a spacer cavity having a first depth relative to an upper surface of a first layer of insulating material positioned adjacent said sidewall spacers.

### Claim 3 (depends on 2)

The method of claim 2, wherein an upper surface of said recessed final gate structure defines, at least in part, a recessed final gate structure cavity having a second depth relative to said upper surface of said first layer of insulating material that is greater than said first depth.

### Claim 4 (depends on 1)

The method of claim 1, wherein forming said etch stop layer comprises forming said etch stop layer from one of Al2O3 or a high-k insulating material.

### Claim 5 (depends on 1)

The method of claim 1, wherein said sidewall spacers are comprised of silicon nitride and said etch stop layer is comprised of a high-k insulating material.

### Claim 6 (depends on 2)

The method of claim 2, further comprising:
forming a second layer of insulating material in a cavity defined by said etch stop layer;
forming a third layer of insulating material above said first and second layers of insulating material;
forming a contact opening in at least said first and third layers of insulating material that exposes a contact region of said transistor; and
forming a conductive contact structure in said contact opening that is conductively coupled to said contact region.

### Claim 7 (depends on 6)

The method of claim 6, wherein, prior to forming said conductive contact structure, the method further comprises:
performing a conformal deposition process to form a dielectric liner layer at least in said contact opening; and
performing an isotropic etching process to remove at least portions of said dielectric liner layer.

### Claim 8 (depends on 7)

The method of claim 7, wherein said dielectric liner layer is one of silicon dioxide or a low-k oxide.

### Claim 9 (depends on 6)

The method of claim 6, wherein said contact region is a source/drain region.

### Claim 10 (depends on 1)

The method of claim 1, wherein said transistor is one of a planar FET or a FinFET.

### Claim 11 (depends on 1)

The method of claim 1, wherein a portion of said etch stop layer has a stepped profile when viewed in cross-section.

### Claim 12

A method, comprising:
forming a final gate structure in a gate cavity that is laterally defined by sidewall spacers positioned in a first layer of insulating material;
removing a portion of said sidewall spacers to define recessed sidewall spacers and a spacer cavity having a first depth relative to an upper surface of said first layer of insulating material;
removing a portion of said final gate structure to define a recessed final gate structure cavity having a second depth relative to said upper surface of said first layer of insulating material that is greater than said first depth; and
forming an etch stop layer on at least said recessed sidewall spacers and said recessed final gate structure, said etch stop layer having a stepped profile when viewed in cross-section.

### Claim 13 (depends on 12)

The method of claim 12, wherein said sidewall spacers are comprised of silicon nitride, said first layer of insulating material is comprised of silicon dioxide and said etch stop layer is comprised of a high-k insulating material.

### Claim 14 (depends on 12)

The method of claim 12, further comprising:
forming a second layer of insulating material in a cavity defined by said etch stop layer;
forming a third layer of insulating material above said first and second layers of insulating material;
forming a contact opening in at least said first and third layers of insulating material that exposes a contact region of said transistor; and
forming a conductive contact structure in said contact opening that is conductively coupled to said contact region.

### Claim 15 (depends on 14)

The method of claim 14, wherein, prior to forming said conductive contact structure, the method further comprises:
performing a conformal deposition process to form a dielectric liner layer at least in said contact opening; and
performing an isotropic etching process to remove at least portions of said dielectric liner layer.

### Claim 16

A transistor device, comprising:
a final gate structure positioned above a semiconducting substrate, said final gate structure having an upper surface that is positioned at a first height level above a surface of said substrate;
sidewall spacers positioned adjacent said final gate structure, said sidewall spacers having an upper surface that is positioned at a second height level above said surface of said substrate, wherein said second height level is greater than said first height level;
an etch stop layer formed on said upper surfaces of said sidewall spacers and said final gate structure;
a layer of insulating material formed above said substrate and said final gate structure; and
a conductive contact positioned in an opening formed in at least said layer of insulating material, said conductive contact being conductively coupled to a contact region of said transistor.

### Claim 17 (depends on 16)

The device of claim 16, wherein said etch stop layer comprises one of Al2O3 or a high-k insulating material.

### Claim 18 (depends on 16)

The device of claim 16, wherein said sidewall spacers are comprised of silicon nitride, said first layer of insulating material is comprised of silicon dioxide and said etch stop layer is comprised of a high-k insulating material.

### Claim 19 (depends on 16)

The device of claim 16, wherein said contact region is a source/drain region.

### Claim 20 (depends on 16)

The device of claim 16, wherein said transistor is one of a planar FET or a FinFET.

### Claim 21 (depends on 16)

The device of claim 16, wherein a portion of said etch stop layer has a stepped profile when viewed in cross-section.

### Claim 22 (depends on 16)

The device of claim 16, wherein said etch stop layer defines a stepped etch stop cavity having at least one layer of insulating material positioned in said etch stop cavity.

### Claim 23 (depends on 16)

The device of claim 16, wherein said etch stop layer defines a stepped etch stop cavity having at least first and second layers of insulating material positioned side by side within said etch stop cavity.

### Claim 24 (depends on 23)

The device of claim 23, wherein said conductive contact is in contact with a side surface of said first layer of insulating material and an upper surface of said second layer of insulating material.

### Claim 25 (depends on 16)

The device of claim 16, wherein said first and second layers of insulating material positioned within said etch stop cavity are comprised of the same materials.

### Claim 26

A transistor device, comprising:
a final gate structure positioned above a semiconducting substrate, said final gate structure having an upper surface that is positioned at a first height level above a surface of said substrate;
sidewall spacers positioned adjacent said final gate structure, said sidewall spacers having an upper surface that is positioned at a second height level above said surface of said substrate, wherein said second height level is greater than said first height level;
an etch stop layer formed on said upper surfaces of said sidewall spacers and said final gate structure, said etch stop layer defining an etch stop cavity having a stepped profile when viewed in cross-section;
a first layer of insulating material positioned in and filling said etch stop cavity;
a second layer of insulating material positioned above said substrate, said first layer of insulating material and said final gate structure; and
a conductive contact positioned in an opening formed in at least said second layer of insulating material, said conductive contact being conductively coupled to a contact region of said transistor.

### Claim 27

A transistor device, comprising:
a final gate structure positioned above a semiconducting substrate, said final gate structure having an upper surface that is positioned at a first height level above a surface of said substrate;
sidewall spacers positioned adjacent said final gate structure, said sidewall spacers having an upper surface that is positioned at a second height level above said surface of said substrate, wherein said second height level is greater than said first height level;
an etch stop layer formed on said upper surfaces of said sidewall spacers and said final gate structure, said etch stop layer defining an etch stop cavity having a stepped profile when viewed in cross-section;
first and second layers of insulating materials positioned side by side in said etch stop cavity;
a third layer of insulating material positioned above said substrate and said final gate structure; and
a conductive contact positioned in an opening formed in at least said third layer of insulating material, said conductive contact being conductively coupled to a contact region of said transistor.

### Claim 28 (depends on 27)

The device of claim 27, wherein said conductive contact is in contact with a side surface of said first layer of insulating material and an upper surface of said second layer of insulating material.

### Claim 29 (depends on 27)

The device of claim 27, wherein said first and second layers of insulating material positioned within said etch stop cavity are comprised of the same materials.