# US 2014/0197467 A1 · High voltage junction field effect transistor structure

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- Number: US 2014/0197467 A1
- Document ID: US20140197467A1
- Status: Published application
- Kind: A1
- Application number: 13/740,725
- Filed: 2013-01-14
- Published: 2014-07-17
- Earliest claimed: 2013-01-14
- Assignees: Macronix International Co., Ltd.
- Applicants: Macronix International Co., Ltd.
- Inventors: WEI-HSUN HSU; SHUO-LUN TU; SHIH-CHIN LIEN; SHYI-YUAN WU
- Web page: https://patentgrep.com/patent/US20140197467A1

## CPC

- H10W 10/00: Isolation regions in semiconductor bodies between components of integrated devices
- H10D 30/83: FETs having PN junction gate electrodes
- H10D 62/116: {adjoining the input or output regions of field-effect devices, e.g. adjoining source or drain regions}
- H10D 62/149: {Source or drain regions of field-effect devices}
- H10D 62/328: {having PN junction gates}
- H10D 84/87: of PN-junction gate FETs
- H10W 10/01: {Manufacture or treatment}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A JFET structure includes a first JFET having a first terminal and a second JFET neighboring with the first JFET. Both JFETs commonly share the first terminal and the first terminal is between the gate of each JFET. The JFET also provides at least one tuning knob to adjust the pinch-off voltage and a tuning knob to adjust the breakdown voltage of the JFET structure. Moreover, the JFET has a buried layer as another tuning knob to adjust the pinch-off voltage of the JFET structure.

## Claims

### Claim 1

A JFET structure, comprising:
a first JFET having a first terminal; and
a second JFET neighboring with the first JFET and commonly sharing the first terminal with the first JFET, wherein the first terminal is between the gate of each JFET.

### Claim 2 (depends on 1)

The JFET structure in claim 1, wherein the commonly shared first terminal is a source or a drain of the JFETs.

### Claim 3 (depends on 1)

The JFET structure in claim 1, wherein the first terminal is equally spaced from the gate of each JFET.

### Claim 4 (depends on 4)

The JFET structure in claim 4, further comprising a first isolation region between the first terminal and the gate

### Claim 5 (depends on 1)

The JFET structure in claim 1, further comprising a well with a first conductivity type, wherein the well is configured to accommodate the first and the second JFET.

### Claim 6 (depends on 5)

The JFET structure in claim 5, wherein the gate comprises:
a gate layer on the well; and
a first doped region of a second conductivity type in the well, wherein the first doped region is coupled with the gate layer.

### Claim 7 (depends on 6)

The JFET structure in claim 6, further comprising a second doped region of the first conductivity type in the well and a second isolation region, wherein the second doped region is separated from the gate by the second isolation region.

### Claim 8 (depends on 6)

The JFET structure in claim 6, wherein the common terminal is a doped region with the first conductivity type.

### Claim 9

A JFET structure providing a plurality of pinch-off channels, wherein the JFET structure comprises:
a substrate of a first conductivity type;
a first JFET having a first terminal;
a second JFET in/on the substrate, wherein the first terminal is commonly shared with the second JFET, in which the first terminal is between the first and second JFET; and
a buried layer of a second conductivity type in the substrate, wherein the buried layer is under the first and second JFET.

### Claim 10 (depends on 9)

The JFET in claim 9, wherein the buried layer is segmented into a plurality of sections.

### Claim 11 (depends on 9)

The JFET in claim 9, wherein each section is separated by an equal space.

### Claim 12 (depends on 9)

The JFET structure in claim 9, wherein the commonly shared first terminal is a source or a drain of the JFETs.

### Claim 13 (depends on 9)

The JFET structure in claim 9, wherein the first terminal is equally spaced from the gateof each JFET.

### Claim 14 (depends on 13)

The JFET structure in claim 13, further comprising a first isolation region between the first terminal and the gate.

### Claim 15 (depends on 9)

The JFET structure in claim 9, further comprising a well with a second conductivity type in the substrate, wherein the well is configured to accommodate the first and the second JFET.

### Claim 16 (depends on 15)

The JFET structure in claim 15, wherein the gate comprises:
a gate layer on the well; and
a body region of a first conductivity type in the well and coupled with the gate layer.

### Claim 17 (depends on 16)

The JFET structure in claim 16, further comprising a second doped region of the second conductivity type in the well and a second isolation region, wherein the second doped region is separated from the gate by the second isolation region.

### Claim 18

A method of manufacturing a JFET structure, wherein the method comprises:
providing a substrate of a first conductivity type;
forming a first JFET and a second JFET in the substrate, wherein the first and second JFET commonly share a first terminal, in which the first terminal is between the gate of each JFET; and
forming a buried layer of the second conductivity type under the first and second JFET.

### Claim 19 (depends on 18)

The method of claim 18, further providing a plurality of spaces between the first terminal and the corresponding gate, wherein each space is equal.

### Claim 20 (depends on 18)

The method of claim 18, further segmenting the buried layer into a plurality of sections.

### Claim 21 (depends on 20)

The method of claim 20, further forming an equal space between each section.

### Claim 22 (depends on 18)

The method of claim 18, further forming an isolation region between a second terminal and a gate of each JFET.

### Claim 23 (depends on 18)

The method of claim 18, further forming a second isolation region between the gate and the first terminal.