# US 2014/0197465 A1 · Nonvolatile memory devices with aligned trench isolation regions

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- Number: US 2014/0197465 A1
- Document ID: US20140197465A1
- Status: Published application
- Kind: A1
- Application number: 14/136,273
- Filed: 2013-12-20
- Published: 2014-07-17
- Earliest claimed: 2013-01-14
- Assignees: Samsung Electronics Co., Ltd.
- Applicants: Samsung Electronics Co., Ltd.
- Inventors: Joon-Young Choi; Sang-Eun Lee; Sam-Jong Choi; Jin-Ho Kim
- Web page: https://patentgrep.com/patent/US20140197465A1

## CPC

- H10D 62/405: {Orientations of crystalline planes}
- H10D 30/681: {having only two programming levels (Floating gate IGFETs programmable by two single electrons H10D30/688)}
- H10D 30/69: IGFETs having charge trapping gate insulators, e.g. MNOS transistors
- H10B 43/35: with cell select transistors, e.g. NAND
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10B: ELECTRONIC MEMORY DEVICES

## Abstract

A nonvolatile memory device includes a substrate, an elongate isolation region including a field insulation film disposed in a trench in the substrate, and a word line crossing the insulation region and including a tunneling insulation layer on an active region of the substrate adjacent the isolation region, a charge storage layer on the tunneling insulation layer and a blocking insulation layer on the charge storage layer. A first plane index of a bottom surface of the trench has a first interface trap density and a second plane index of a sidewall of the trench has a second interface trap density equal to or less than the first interface trap density. In some embodiments, the first plane index may be (100) and the second plane index may be (100) or (310).

## Claims

### Claim 1

A nonvolatile memory device comprising:
a substrate;
an elongate isolation region comprising a field insulation film disposed in a trench in the substrate; and
a word line crossing the insulation region and comprising a tunneling insulation layer on an active region of the substrate adjacent the isolation region, a charge storage layer on the tunneling insulation layer and a blocking insulation layer on the charge storage layer,
wherein a first plane index of a bottom surface of the trench has a first interface trap density and wherein a second plane index of a sidewall of the trench has a second interface trap density equal to or less than the first interface trap density.

### Claim 2 (depends on 1)

The nonvolatile memory device of claim 1, wherein the first plane index is (100).

### Claim 3 (depends on 2)

The nonvolatile memory device of claim 2, wherein the second plane index is (100) or (310).

### Claim 4 (depends on 1)

The nonvolatile memory device of claim 1, wherein the substrate has an alignment basis region having a plane index corresponding to a rotation of α° from a plane having a plane index (110), where 0<α≦45 or −45≦α<0.

### Claim 5 (depends on 2)

The nonvolatile memory device of claim 2, wherein α is 18.5 or −18.5.

### Claim 6 (depends on 1)

The nonvolatile memory device of claim 1, wherein a plane index of an alignment basis region of the substrate is (100).

### Claim 7 (depends on 2)

The nonvolatile memory device of claim 2, wherein the word line extends in a <100> direction.

### Claim 8 (depends on 1)

The nonvolatile memory device of claim 1, wherein a separate junction area is not formed in the active region.

### Claim 9 (depends on 2)

The nonvolatile memory device of claim 2, wherein the substrate is a silicon on insulator (SOI) substrate.

### Claim 10 (depends on 1)

The nonvolatile memory device of claim 1, wherein the substrate comprises a base substrate and an epitaxial layer disposed on the base substrate.

### Claim 11

A nonvolatile memory device comprising:
a substrate having an alignment basis region having a plane index corresponding to a rotation of α° from a plane having a plane index (110), where 0<α≦45 or −45≦α<0;
an elongate isolation region comprising a field insulation film disposed in a trench in the substrate; and
a word line crossing the insulation region and comprising a tunneling insulation layer on an active region of the substrate adjacent the isolation region, a charge storage layer on the tunneling insulation layer and a blocking insulation layer on the charge storage layer,

### Claim 12 (depends on 11)

The nonvolatile memory device of claim 11, wherein α is 18.5 or −18.5.

### Claim 13 (depends on 11)

The nonvolatile memory device of claim 11, wherein a first plane index of a bottom surface of the trench is (100) and wherein a second plane index of a sidewall of trench is (100) or (310).

### Claim 14 (depends on 11)

The nonvolatile memory device of claim 11, wherein a separate junction area is not formed in the active region.

### Claim 15

A nonvolatile memory device comprising:
a substrate having an alignment basis region with a plane index of (100);
an elongate isolation region in the substrate and defining an elongate active region; and
a word line crossing the active region and comprising a tunneling insulation layer on the active region, a charge storage layer on the tunneling insulation layer and a blocking insulation layer on the charge storage layer,
wherein the active region and the word line linearly extend along respective different <100> directions.

### Claim 16 (depends on 15)

The nonvolatile memory device of claim 15, wherein the isolation region comprises field insulation film in a trench, wherein a first plane index of a bottom surface of the trench has a first interface trap density and wherein a second plane index of a sidewall of the trench has a second interface trap density equal to or less than the first interface trap density.

### Claim 17 (depends on 16)

The nonvolatile memory device of claim 16, wherein the first plane index is (100) and wherein the second plane index is (100) or (310).